From patchwork Sun Sep 1 21:22:40 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antony Pavlov X-Patchwork-Id: 271648 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0E24F2C0084 for ; Mon, 2 Sep 2013 07:26:14 +1000 (EST) Received: from localhost ([::1]:35784 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGF9v-0005k4-VO for incoming@patchwork.ozlabs.org; Sun, 01 Sep 2013 17:26:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45472) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGF97-0005cq-9v for qemu-devel@nongnu.org; Sun, 01 Sep 2013 17:25:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VGF93-0005Fn-05 for qemu-devel@nongnu.org; Sun, 01 Sep 2013 17:25:21 -0400 Received: from mail-la0-x229.google.com ([2a00:1450:4010:c03::229]:58180) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGF92-0005Ff-J5 for qemu-devel@nongnu.org; Sun, 01 Sep 2013 17:25:16 -0400 Received: by mail-la0-f41.google.com with SMTP id ec20so3100040lab.28 for ; Sun, 01 Sep 2013 14:25:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2neP4zbCWvS1rxkrMTZjj8VwfcSqTTMJTbCOAlCYvu8=; b=a2R3oKfpVGmwXxtmySkqsF+Y0vDFvOVh8sp28OxfiQEprHnGFv6h4PdR4otiSJsyZO r2VlUIVeNxa+bCZLC2xJRvPmX7ykIPFvviJDVhVhlILnZAQppG3CUlcTa+wcI+Z1sHbh /RKF3Ji3Uo5dISzw1qdwM69yGGZmWpK9lK2jHmMjx2+rH8V4OiI2Tbp01zyqXQkNv6+E WpSrKndlutir/wjshBY8d/A7EAHYFmeJn7+wSpz1IjlyTOItRqPcsz6tPt7FkeOeWgSN XvlYgGpujunzbkijknzBGuybDHephhejZ6u6Qfr6sPoO36yrzAD9xE/InfuxmeJwI9BZ d1HQ== X-Received: by 10.152.5.66 with SMTP id q2mr18661060laq.13.1378070715552; Sun, 01 Sep 2013 14:25:15 -0700 (PDT) Received: from localhost.localdomain (ppp37-190-57-26.pppoe.spdop.ru. [37.190.57.26]) by mx.google.com with ESMTPSA id u20sm4348379lbh.7.1969.12.31.16.00.00 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 01 Sep 2013 14:25:14 -0700 (PDT) From: Antony Pavlov To: qemu-devel@nongnu.org Date: Mon, 2 Sep 2013 01:22:40 +0400 Message-Id: <1378070562-14777-4-git-send-email-antonynpavlov@gmail.com> X-Mailer: git-send-email 1.8.4.rc3 In-Reply-To: <1378070562-14777-1-git-send-email-antonynpavlov@gmail.com> References: <1378070562-14777-1-git-send-email-antonynpavlov@gmail.com> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2a00:1450:4010:c03::229 Cc: Alex Dumitrache , Peter Crosthwaite , Giovanni Condello , g3gg0 , Peter Maydell , Paul Brook , Paolo Bonzini , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Antony Pavlov Subject: [Qemu-devel] [RFC v2 3/5] hw/arm/digic: add timer support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Antony Pavlov --- hw/arm/digic.c | 25 ++++++++++ hw/timer/Makefile.objs | 1 + hw/timer/digic-timer.c | 122 +++++++++++++++++++++++++++++++++++++++++++++++++ hw/timer/digic-timer.h | 19 ++++++++ include/hw/arm/digic.h | 7 +++ 5 files changed, 174 insertions(+) create mode 100644 hw/timer/digic-timer.c create mode 100644 hw/timer/digic-timer.h diff --git a/hw/arm/digic.c b/hw/arm/digic.c index 5e737ee..0025f15 100644 --- a/hw/arm/digic.c +++ b/hw/arm/digic.c @@ -30,21 +30,46 @@ static void digic_init(Object *obj) { DigicState *s = DIGIC(obj); + DeviceState *dev; + int i; object_initialize(&s->cpu, "arm946-" TYPE_ARM_CPU); object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL); + + for (i = 0; i < DIGIC4_NB_TIMERS; i++) { + char name[9]; + + object_initialize(&s->timer[i], TYPE_DIGIC_TIMER); + dev = DEVICE(&s->timer[i]); + qdev_set_parent_bus(dev, sysbus_get_default()); + snprintf(name, 9, "timer[%d]", i); + object_property_add_child(obj, name, OBJECT(&s->timer[i]), NULL); + } } static void digic_realize(DeviceState *dev, Error **errp) { DigicState *s = DIGIC(dev); Error *err = NULL; + SysBusDevice *sbd; + int i; object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); return; } + + for (i = 0; i < DIGIC4_NB_TIMERS; i++) { + object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + + sbd = SYS_BUS_DEVICE(&s->timer[i]); + sysbus_mmio_map(sbd, 0, DIGIC4_TIMER_BASE(i)); + } } static void digic_class_init(ObjectClass *oc, void *data) diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs index eca5905..5479aee 100644 --- a/hw/timer/Makefile.objs +++ b/hw/timer/Makefile.objs @@ -25,5 +25,6 @@ obj-$(CONFIG_OMAP) += omap_synctimer.o obj-$(CONFIG_PXA2XX) += pxa2xx_timer.o obj-$(CONFIG_SH4) += sh_timer.o obj-$(CONFIG_TUSB6010) += tusb6010.o +obj-$(CONFIG_DIGIC) += digic-timer.o obj-$(CONFIG_MC146818RTC) += mc146818rtc.o diff --git a/hw/timer/digic-timer.c b/hw/timer/digic-timer.c new file mode 100644 index 0000000..c6cf7ee --- /dev/null +++ b/hw/timer/digic-timer.c @@ -0,0 +1,122 @@ +/* + * QEMU model of the Canon Digic timer block. + * + * Copyright (C) 2013 Antony Pavlov + * + * This model is based on reverse engineering efforts + * made by CHDK (http://chdk.wikia.com) and + * Magic Lantern (http://www.magiclantern.fm) projects + * contributors. + * + * See "Timer/Clock Module" docs here: + * http://magiclantern.wikia.com/wiki/Register_Map + * + * The QEMU model of the OSTimer in PKUnity SoC by Guan Xuetao + * is used as a template. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + */ + +#include "hw/sysbus.h" +#include "hw/ptimer.h" +#include "qemu/main-loop.h" + +#include "hw/timer/digic-timer.h" + +#ifdef DEBUG_DIGIC_TIMER +#define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__) +#else +#define DPRINTF(fmt, ...) do {} while (0) +#endif + +# define DIGIC_TIMER_CONTROL 0x00 +# define DIGIC_TIMER_VALUE 0x0c + +static uint64_t digic_timer_read(void *opaque, hwaddr offset, + unsigned size) +{ + DigicTimerState *s = opaque; + uint32_t ret = 0; + + switch (offset) { + case DIGIC_TIMER_VALUE: + ret = (uint32_t)ptimer_get_count(s->ptimer); + ret = ret & 0xffff; + break; + default: + DPRINTF("Bad offset %x\n", (int)offset); + } + + DPRINTF("offset 0x%x, value 0x%x\n", offset, ret); + return ret; +} + +static void digic_timer_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + DigicTimerState *s = opaque; + + /* FIXME: just now we ignore timer enable bit */ + ptimer_set_limit(s->ptimer, 0x0000ffff, 1); + ptimer_run(s->ptimer, 1); +} + +static const MemoryRegionOps digic_timer_ops = { + .read = digic_timer_read, + .write = digic_timer_write, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +static void digic_timer_tick(void *opaque) +{ + DigicTimerState *s = opaque; + + ptimer_run(s->ptimer, 1); +} + +static void digic_timer_init(Object *obj) +{ + DigicTimerState *s = DIGIC_TIMER(obj); + + s->bh = qemu_bh_new(digic_timer_tick, s); + s->ptimer = ptimer_init(s->bh); + + /* FIXME: there is no documentation on Digic timer + * frequency setup so let's it always run on 1 MHz + * */ + ptimer_set_freq(s->ptimer, 1 * 1000 * 1000); + + memory_region_init_io(&s->iomem, OBJECT(s), &digic_timer_ops, s, + TYPE_DIGIC_TIMER, 0x100); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); +} + +static const TypeInfo digic_timer_info = { + .name = TYPE_DIGIC_TIMER, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(DigicTimerState), + .instance_init = digic_timer_init, +}; + +static void digic_timer_register_type(void) +{ + type_register_static(&digic_timer_info); +} + +type_init(digic_timer_register_type) diff --git a/hw/timer/digic-timer.h b/hw/timer/digic-timer.h new file mode 100644 index 0000000..6483516 --- /dev/null +++ b/hw/timer/digic-timer.h @@ -0,0 +1,19 @@ +#ifndef HW_TIMER_DIGIC_TIMER_H +#define HW_TIMER_DIGIC_TIMER_H + +#include "hw/sysbus.h" +#include "qemu/typedefs.h" +#include "hw/ptimer.h" + +#define TYPE_DIGIC_TIMER "digic-timer" +#define DIGIC_TIMER(obj) OBJECT_CHECK(DigicTimerState, (obj), TYPE_DIGIC_TIMER) + +typedef struct DigicTimerState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + QEMUBH *bh; + ptimer_state *ptimer; +} DigicTimerState; + +#endif /* HW_TIMER_DIGIC_TIMER_H */ diff --git a/include/hw/arm/digic.h b/include/hw/arm/digic.h index 0ef4723..472d7d7 100644 --- a/include/hw/arm/digic.h +++ b/include/hw/arm/digic.h @@ -10,6 +10,11 @@ #include "cpu-qom.h" +#include "hw/timer/digic-timer.h" + +#define DIGIC4_NB_TIMERS 3 +#define DIGIC4_TIMER_BASE(n) (0xc0210000 + n * 0x100) + #define TYPE_DIGIC "digic" #define DIGIC(obj) OBJECT_CHECK(DigicState, (obj), TYPE_DIGIC) @@ -18,6 +23,8 @@ typedef struct DigicState { Object parent_obj; ARMCPU cpu; + + DigicTimerState timer[DIGIC4_NB_TIMERS]; } DigicState; #endif /* __DIGIC_H__ */