From patchwork Thu Aug 29 20:51:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 270942 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id F13922C0095 for ; Fri, 30 Aug 2013 06:53:03 +1000 (EST) Received: from localhost ([::1]:45712 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VF9DB-0004B3-Mw for incoming@patchwork.ozlabs.org; Thu, 29 Aug 2013 16:53:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38780) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VF9Bx-0002Yy-8i for qemu-devel@nongnu.org; Thu, 29 Aug 2013 16:51:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VF9Bw-0004BJ-By for qemu-devel@nongnu.org; Thu, 29 Aug 2013 16:51:45 -0400 Received: from hall.aurel32.net ([2001:470:1f0b:4a8::1]:40406) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VF9Bw-0004BF-4m for qemu-devel@nongnu.org; Thu, 29 Aug 2013 16:51:44 -0400 Received: from [2001:470:d4ed:1:2db:dfff:fe14:52d] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.2:DHE_RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1VF9Bv-0002B9-5I; Thu, 29 Aug 2013 22:51:43 +0200 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1VF9Be-0006Ic-V3; Thu, 29 Aug 2013 22:51:26 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Thu, 29 Aug 2013 22:51:25 +0200 Message-Id: <1377809485-24004-4-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1377809485-24004-1-git-send-email-aurelien@aurel32.net> References: <1377809485-24004-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:470:1f0b:4a8::1 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH v3 3/3] tcg/mips: only enable ext8s/ext16s ops on MIPS32R2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On MIPS ext8s and ext16s ops are implemented with a dedicated instruction only on MIPS32R2, otherwise the same kind of implementation than at TCG level (shift left followed by shift right) is used. Change that by only implementing the ext8s and ext16s ops on MIPS32R2 so that optimizations can be done by the optimizer. Use an inline version to avoid having to test again for MIPS32R2 instructions. Keep the shift implementation for the ld/st routines. Signed-off-by: Aurelien Jarno --- tcg/mips/tcg-target.c | 4 ++-- tcg/mips/tcg-target.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index daaf722..f32bea7 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -1515,10 +1515,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_ext8s_i32: - tcg_out_ext8s(s, args[0], args[1]); + tcg_out_opc_reg(s, OPC_SEB, args[0], 0, args[1]); break; case INDEX_op_ext16s_i32: - tcg_out_ext16s(s, args[0], args[1]); + tcg_out_opc_reg(s, OPC_SEH, args[0], 0, args[1]); break; case INDEX_op_deposit_i32: diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 43072e3..76ee831 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -105,8 +105,6 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_rem_i32 1 #define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_nor_i32 1 -#define TCG_TARGET_HAS_ext8s_i32 1 -#define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_andc_i32 0 #define TCG_TARGET_HAS_orc_i32 0 #define TCG_TARGET_HAS_eqv_i32 0 @@ -118,6 +116,8 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_bswap16_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_bswap32_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions +#define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions +#define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions /* optional instructions automatically implemented */