From patchwork Thu Jun 20 13:08:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Michael S. Tsirkin" X-Patchwork-Id: 252907 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4F24A2C023D for ; Thu, 20 Jun 2013 23:09:17 +1000 (EST) Received: from localhost ([::1]:36863 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Upebz-0006mD-4K for incoming@patchwork.ozlabs.org; Thu, 20 Jun 2013 09:09:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37777) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UpeaU-0004lF-NR for qemu-devel@nongnu.org; Thu, 20 Jun 2013 09:07:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UpeaN-0007NJ-Pl for qemu-devel@nongnu.org; Thu, 20 Jun 2013 09:07:42 -0400 Received: from mx1.redhat.com ([209.132.183.28]:18294) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UpeaN-0007NB-HQ for qemu-devel@nongnu.org; Thu, 20 Jun 2013 09:07:35 -0400 Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id r5KD7Yff031976 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Thu, 20 Jun 2013 09:07:34 -0400 Received: from redhat.com (vpn-200-33.tlv.redhat.com [10.35.200.33]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with SMTP id r5KD7UxN025633; Thu, 20 Jun 2013 09:07:31 -0400 Date: Thu, 20 Jun 2013 16:08:19 +0300 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Message-ID: <1371730033-5554-4-git-send-email-mst@redhat.com> References: <1371730033-5554-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1371730033-5554-1-git-send-email-mst@redhat.com> X-Mutt-Fcc: =sent X-Scanned-By: MIMEDefang 2.67 on 10.5.11.11 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: Paolo Bonzini , Anthony Liguori , =?us-ascii?B?PT9VVEYtOD9xP0FuZHJlYXM9MjBGPUMzPUE0cmJlcj89?= , Eduardo Habkost , Igor Mammedov Subject: [Qemu-devel] [PULL 03/21] pc: pass PCI hole ranges to Guests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Guest currently has to jump through lots of hoops to guess the PCI hole ranges. It's fragile, and makes us change BIOS each time we add a new chipset. Let's report the window in a ROM file, to make BIOS do exactly what QEMU intends. Signed-off-by: Michael S. Tsirkin --- hw/i386/pc.c | 26 ++++++++++++++++++++++++++ hw/i386/pc_piix.c | 16 +++++++++++++++- hw/i386/pc_q35.c | 12 ++++++++++-- include/hw/i386/pc.h | 1 + 4 files changed, 52 insertions(+), 3 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index c685ee8..e1ed760 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -990,6 +990,31 @@ void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge) } } +/* pci-info ROM file. Little endian format */ +typedef struct PcRomPciInfo { + uint64_t w32_min; + uint64_t w32_max; + uint64_t w64_min; + uint64_t w64_max; +} PcRomPciInfo; + +static void pc_fw_cfg_guest_info(PcGuestInfo *guest_info) +{ + PcRomPciInfo *info; + if (!guest_info->has_pci_info) { + return; + } + + info = g_malloc(sizeof *info); + info->w32_min = cpu_to_le64(guest_info->pci_info.w32.begin); + info->w32_max = cpu_to_le64(guest_info->pci_info.w32.end); + info->w64_min = cpu_to_le64(guest_info->pci_info.w64.begin); + info->w64_max = cpu_to_le64(guest_info->pci_info.w64.end); + /* Pass PCI hole info to guest via a side channel. + * Required so guest PCI enumeration does the right thing. */ + fw_cfg_add_file(guest_info->fw_cfg, "etc/pci-info", info, sizeof *info); +} + typedef struct PcGuestInfoState { PcGuestInfo info; Notifier machine_done; @@ -1001,6 +1026,7 @@ void pc_guest_info_machine_done(Notifier *notifier, void *data) PcGuestInfoState *guest_info_state = container_of(notifier, PcGuestInfoState, machine_done); + pc_fw_cfg_guest_info(&guest_info_state->info); } PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index a70a0d9..d87da95 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -57,6 +57,7 @@ static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 }; static const int ide_irq[MAX_IDE_BUS] = { 14, 15 }; static bool has_pvpanic = true; +static bool has_pci_info = true; /* PC hardware initialisation */ static void pc_init1(MemoryRegion *system_memory, @@ -121,6 +122,7 @@ static void pc_init1(MemoryRegion *system_memory, } guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size); + guest_info->has_pci_info = has_pci_info; /* Set PCI window size the way seabios has always done it. */ /* Power of 2 so bios can cover it with a single MTRR */ @@ -258,8 +260,15 @@ static void pc_init_pci(QEMUMachineInitArgs *args) initrd_filename, cpu_model, 1, 1); } +static void pc_init_pci_1_5(QEMUMachineInitArgs *args) +{ + has_pci_info = false; + pc_init_pci(args); +} + static void pc_init_pci_1_4(QEMUMachineInitArgs *args) { + has_pci_info = false; has_pvpanic = false; x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE); pc_init_pci(args); @@ -267,6 +276,7 @@ static void pc_init_pci_1_4(QEMUMachineInitArgs *args) static void pc_init_pci_1_3(QEMUMachineInitArgs *args) { + has_pci_info = false; enable_compat_apic_id_mode(); has_pvpanic = false; pc_init_pci(args); @@ -275,6 +285,7 @@ static void pc_init_pci_1_3(QEMUMachineInitArgs *args) /* PC machine init function for pc-1.1 to pc-1.2 */ static void pc_init_pci_1_2(QEMUMachineInitArgs *args) { + has_pci_info = false; disable_kvm_pv_eoi(); enable_compat_apic_id_mode(); has_pvpanic = false; @@ -284,6 +295,7 @@ static void pc_init_pci_1_2(QEMUMachineInitArgs *args) /* PC machine init function for pc-0.14 to pc-1.0 */ static void pc_init_pci_1_0(QEMUMachineInitArgs *args) { + has_pci_info = false; disable_kvm_pv_eoi(); enable_compat_apic_id_mode(); has_pvpanic = false; @@ -300,6 +312,7 @@ static void pc_init_pci_no_kvmclock(QEMUMachineInitArgs *args) const char *initrd_filename = args->initrd_filename; const char *boot_device = args->boot_device; has_pvpanic = false; + has_pci_info = false; disable_kvm_pv_eoi(); enable_compat_apic_id_mode(); pc_init1(get_system_memory(), @@ -318,6 +331,7 @@ static void pc_init_isa(QEMUMachineInitArgs *args) const char *initrd_filename = args->initrd_filename; const char *boot_device = args->boot_device; has_pvpanic = false; + has_pci_info = false; if (cpu_model == NULL) cpu_model = "486"; disable_kvm_pv_eoi(); @@ -353,7 +367,7 @@ static QEMUMachine pc_i440fx_machine_v1_6 = { static QEMUMachine pc_i440fx_machine_v1_5 = { .name = "pc-i440fx-1.5", .desc = "Standard PC (i440FX + PIIX, 1996)", - .init = pc_init_pci, + .init = pc_init_pci_1_5, .hot_add_cpu = pc_hot_add_cpu, .max_cpus = 255, .compat_props = (GlobalProperty[]) { diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index a13acf2..5b92160 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -47,6 +47,7 @@ #define MAX_SATA_PORTS 6 static bool has_pvpanic = true; +static bool has_pci_info = true; /* PC hardware initialisation */ static void pc_q35_init(QEMUMachineInitArgs *args) @@ -107,6 +108,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args) } guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size); + guest_info->has_pci_info = has_pci_info; /* allocate ram and load rom/bios */ if (!xen_enabled()) { @@ -212,11 +214,17 @@ static void pc_q35_init(QEMUMachineInitArgs *args) } } +static void pc_q35_init_1_5(QEMUMachineInitArgs *args) +{ + has_pci_info = false; + pc_q35_init(args); +} + static void pc_q35_init_1_4(QEMUMachineInitArgs *args) { has_pvpanic = false; x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE); - pc_q35_init(args); + pc_q35_init_1_5(args); } static QEMUMachine pc_q35_machine_v1_6 = { @@ -232,7 +240,7 @@ static QEMUMachine pc_q35_machine_v1_6 = { static QEMUMachine pc_q35_machine_v1_5 = { .name = "pc-q35-1.5", .desc = "Standard PC (Q35 + ICH9, 2009)", - .init = pc_q35_init, + .init = pc_q35_init_1_5, .hot_add_cpu = pc_hot_add_cpu, .max_cpus = 255, .compat_props = (GlobalProperty[]) { diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 6cb06fe..ba9ba1a 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -20,6 +20,7 @@ typedef struct PcPciInfo { struct PcGuestInfo { PcPciInfo pci_info; + bool has_pci_info; FWCfgState *fw_cfg; };