From patchwork Tue May 28 08:21:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liguang X-Patchwork-Id: 246751 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 733D12C013D for ; Tue, 28 May 2013 18:42:47 +1000 (EST) Received: from localhost ([::1]:39482 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UhFEF-0000ee-EB for incoming@patchwork.ozlabs.org; Tue, 28 May 2013 04:25:59 -0400 Received: from eggs.gnu.org ([208.118.235.92]:59876) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UhFC1-00063m-WD for qemu-devel@nongnu.org; Tue, 28 May 2013 04:23:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UhFBs-0001W1-Et for qemu-devel@nongnu.org; Tue, 28 May 2013 04:23:41 -0400 Received: from [222.73.24.84] (port=40179 helo=song.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UhFBo-0001VT-M3 for qemu-devel@nongnu.org; Tue, 28 May 2013 04:23:32 -0400 X-IronPort-AV: E=Sophos;i="4.87,756,1363104000"; d="scan'208";a="7388309" Received: from unknown (HELO tang.cn.fujitsu.com) ([10.167.250.3]) by song.cn.fujitsu.com with ESMTP; 28 May 2013 16:20:35 +0800 Received: from fnstmail02.fnst.cn.fujitsu.com (tang.cn.fujitsu.com [127.0.0.1]) by tang.cn.fujitsu.com (8.14.3/8.13.1) with ESMTP id r4S8NOJq015522; Tue, 28 May 2013 16:23:25 +0800 Received: from liguang.fnst.cn.fujitsu.com ([10.167.233.147]) by fnstmail02.fnst.cn.fujitsu.com (Lotus Domino Release 8.5.3) with ESMTP id 2013052816215674-1588292 ; Tue, 28 May 2013 16:21:56 +0800 From: liguang To: qemu-devel@nongnu.org Date: Tue, 28 May 2013 16:21:01 +0800 Message-Id: <1369729270-9991-3-git-send-email-lig.fnst@cn.fujitsu.com> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1369729270-9991-1-git-send-email-lig.fnst@cn.fujitsu.com> References: <1369729270-9991-1-git-send-email-lig.fnst@cn.fujitsu.com> X-MIMETrack: Itemize by SMTP Server on mailserver/fnst(Release 8.5.3|September 15, 2011) at 2013/05/28 16:21:56, Serialize by Router on mailserver/fnst(Release 8.5.3|September 15, 2011) at 2013/05/28 16:21:57, Serialize complete at 2013/05/28 16:21:57 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 222.73.24.84 Cc: Peter Maydell , Anthony Liguori , Eduardo Habkost , Blue Swirl , Igor Mammedov , Paolo Bonzini , =?UTF-8?q?Andreas=20F=C3=A4rber?= , liguang , Richard Henderson Subject: [Qemu-devel] [PATCH v4 03/12] target-i386/helper: remove ECX macro X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: liguang --- target-i386/cpu.h | 2 -- target-i386/mem_helper.c | 4 ++-- target-i386/misc_helper.c | 44 ++++++++++++++++++++++---------------------- target-i386/seg_helper.c | 18 +++++++++--------- target-i386/smm_helper.c | 8 ++++---- target-i386/svm_helper.c | 10 +++++----- 6 files changed, 42 insertions(+), 44 deletions(-) diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 28ff02d..b3c6fcb 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -1101,8 +1101,6 @@ static inline int cpu_mmu_index (CPUX86State *env) ? MMU_KSMAP_IDX : MMU_KERNEL_IDX; } -#undef ECX -#define ECX (env->regs[R_ECX]) #undef EDX #define EDX (env->regs[R_EDX]) #undef ESP diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c index 6370fb5..41ac847 100644 --- a/target-i386/mem_helper.c +++ b/target-i386/mem_helper.c @@ -46,7 +46,7 @@ void helper_cmpxchg8b(CPUX86State *env, target_ulong a0) eflags = cpu_cc_compute_all(env, CC_OP); d = cpu_ldq_data(env, a0); if (d == (((uint64_t)EDX << 32) | (uint32_t)env->regs[R_EAX])) { - cpu_stq_data(env, a0, ((uint64_t)ECX << 32) | (uint32_t)env->regs[R_EBX]); + cpu_stq_data(env, a0, ((uint64_t)env->regs[R_ECX] << 32) | (uint32_t)env->regs[R_EBX]); eflags |= CC_Z; } else { /* always do the store */ @@ -72,7 +72,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a0) d1 = cpu_ldq_data(env, a0 + 8); if (d0 == env->regs[R_EAX] && d1 == EDX) { cpu_stq_data(env, a0, env->regs[R_EBX]); - cpu_stq_data(env, a0 + 8, ECX); + cpu_stq_data(env, a0 + 8, env->regs[R_ECX]); eflags |= CC_Z; } else { /* always do the store */ diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c index d7be4f4..b0afffe 100644 --- a/target-i386/misc_helper.c +++ b/target-i386/misc_helper.c @@ -122,10 +122,10 @@ void helper_cpuid(CPUX86State *env) cpu_svm_check_intercept_param(env, SVM_EXIT_CPUID, 0); - cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)ECX, &eax, &ebx, &ecx, &edx); + cpu_x86_cpuid(env, (uint32_t)env->regs[R_EAX], (uint32_t)env->regs[R_ECX], &eax, &ebx, &ecx, &edx); env->regs[R_EAX] = eax; env->regs[R_EBX] = ebx; - ECX = ecx; + env->regs[R_ECX] = ecx; EDX = edx; } @@ -241,7 +241,7 @@ void helper_rdtsc(CPUX86State *env) void helper_rdtscp(CPUX86State *env) { helper_rdtsc(env); - ECX = (uint32_t)(env->tsc_aux); + env->regs[R_ECX] = (uint32_t)(env->tsc_aux); } void helper_rdpmc(CPUX86State *env) @@ -273,7 +273,7 @@ void helper_wrmsr(CPUX86State *env) val = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)EDX) << 32); - switch ((uint32_t)ECX) { + switch ((uint32_t)env->regs[R_ECX]) { case MSR_IA32_SYSENTER_CS: env->sysenter_cs = val & 0xffff; break; @@ -350,7 +350,7 @@ void helper_wrmsr(CPUX86State *env) case MSR_MTRRphysBase(5): case MSR_MTRRphysBase(6): case MSR_MTRRphysBase(7): - env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysBase(0)) / 2].base = val; + env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysBase(0)) / 2].base = val; break; case MSR_MTRRphysMask(0): case MSR_MTRRphysMask(1): @@ -360,14 +360,14 @@ void helper_wrmsr(CPUX86State *env) case MSR_MTRRphysMask(5): case MSR_MTRRphysMask(6): case MSR_MTRRphysMask(7): - env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysMask(0)) / 2].mask = val; + env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysMask(0)) / 2].mask = val; break; case MSR_MTRRfix64K_00000: - env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix64K_00000] = val; + env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix64K_00000] = val; break; case MSR_MTRRfix16K_80000: case MSR_MTRRfix16K_A0000: - env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix16K_80000 + 1] = val; + env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix16K_80000 + 1] = val; break; case MSR_MTRRfix4K_C0000: case MSR_MTRRfix4K_C8000: @@ -377,7 +377,7 @@ void helper_wrmsr(CPUX86State *env) case MSR_MTRRfix4K_E8000: case MSR_MTRRfix4K_F0000: case MSR_MTRRfix4K_F8000: - env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix4K_C0000 + 3] = val; + env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix4K_C0000 + 3] = val; break; case MSR_MTRRdefType: env->mtrr_deftype = val; @@ -398,9 +398,9 @@ void helper_wrmsr(CPUX86State *env) env->msr_ia32_misc_enable = val; break; default: - if ((uint32_t)ECX >= MSR_MC0_CTL - && (uint32_t)ECX < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) { - uint32_t offset = (uint32_t)ECX - MSR_MC0_CTL; + if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL + && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) { + uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL; if ((offset & 0x3) != 0 || (val == 0 || val == ~(uint64_t)0)) { env->mce_banks[offset] = val; @@ -418,7 +418,7 @@ void helper_rdmsr(CPUX86State *env) cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 0); - switch ((uint32_t)ECX) { + switch ((uint32_t)env->regs[R_ECX]) { case MSR_IA32_SYSENTER_CS: val = env->sysenter_cs; break; @@ -480,7 +480,7 @@ void helper_rdmsr(CPUX86State *env) case MSR_MTRRphysBase(5): case MSR_MTRRphysBase(6): case MSR_MTRRphysBase(7): - val = env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysBase(0)) / 2].base; + val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysBase(0)) / 2].base; break; case MSR_MTRRphysMask(0): case MSR_MTRRphysMask(1): @@ -490,14 +490,14 @@ void helper_rdmsr(CPUX86State *env) case MSR_MTRRphysMask(5): case MSR_MTRRphysMask(6): case MSR_MTRRphysMask(7): - val = env->mtrr_var[((uint32_t)ECX - MSR_MTRRphysMask(0)) / 2].mask; + val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - MSR_MTRRphysMask(0)) / 2].mask; break; case MSR_MTRRfix64K_00000: val = env->mtrr_fixed[0]; break; case MSR_MTRRfix16K_80000: case MSR_MTRRfix16K_A0000: - val = env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix16K_80000 + 1]; + val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix16K_80000 + 1]; break; case MSR_MTRRfix4K_C0000: case MSR_MTRRfix4K_C8000: @@ -507,7 +507,7 @@ void helper_rdmsr(CPUX86State *env) case MSR_MTRRfix4K_E8000: case MSR_MTRRfix4K_F0000: case MSR_MTRRfix4K_F8000: - val = env->mtrr_fixed[(uint32_t)ECX - MSR_MTRRfix4K_C0000 + 3]; + val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - MSR_MTRRfix4K_C0000 + 3]; break; case MSR_MTRRdefType: val = env->mtrr_deftype; @@ -538,9 +538,9 @@ void helper_rdmsr(CPUX86State *env) val = env->msr_ia32_misc_enable; break; default: - if ((uint32_t)ECX >= MSR_MC0_CTL - && (uint32_t)ECX < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) { - uint32_t offset = (uint32_t)ECX - MSR_MC0_CTL; + if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL + && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + (4 * env->mcg_cap & 0xff)) { + uint32_t offset = (uint32_t)env->regs[R_ECX] - MSR_MC0_CTL; val = env->mce_banks[offset]; break; } @@ -576,7 +576,7 @@ void helper_hlt(CPUX86State *env, int next_eip_addend) void helper_monitor(CPUX86State *env, target_ulong ptr) { - if ((uint32_t)ECX != 0) { + if ((uint32_t)env->regs[R_ECX] != 0) { raise_exception(env, EXCP0D_GPF); } /* XXX: store address? */ @@ -588,7 +588,7 @@ void helper_mwait(CPUX86State *env, int next_eip_addend) CPUState *cs; X86CPU *cpu; - if ((uint32_t)ECX != 0) { + if ((uint32_t)env->regs[R_ECX] != 0) { raise_exception(env, EXCP0D_GPF); } cpu_svm_check_intercept_param(env, SVM_EXIT_MWAIT, 0); diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c index b3c087f..60d723a 100644 --- a/target-i386/seg_helper.c +++ b/target-i386/seg_helper.c @@ -325,7 +325,7 @@ static void switch_tss(CPUX86State *env, int tss_selector, cpu_stl_kernel(env, env->tr.base + 0x20, next_eip); cpu_stl_kernel(env, env->tr.base + 0x24, old_eflags); cpu_stl_kernel(env, env->tr.base + (0x28 + 0 * 4), env->regs[R_EAX]); - cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), ECX); + cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), env->regs[R_ECX]); cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), EDX); cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX]); cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), ESP); @@ -341,7 +341,7 @@ static void switch_tss(CPUX86State *env, int tss_selector, cpu_stw_kernel(env, env->tr.base + 0x0e, next_eip); cpu_stw_kernel(env, env->tr.base + 0x10, old_eflags); cpu_stw_kernel(env, env->tr.base + (0x12 + 0 * 2), env->regs[R_EAX]); - cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), ECX); + cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), env->regs[R_ECX]); cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), EDX); cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX]); cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), ESP); @@ -397,7 +397,7 @@ static void switch_tss(CPUX86State *env, int tss_selector, cpu_load_eflags(env, new_eflags, eflags_mask); /* XXX: what to do in 16 bit case? */ env->regs[R_EAX] = new_regs[0]; - ECX = new_regs[1]; + env->regs[R_ECX] = new_regs[1]; EDX = new_regs[2]; env->regs[R_EBX] = new_regs[3]; ESP = new_regs[4]; @@ -949,7 +949,7 @@ void helper_syscall(CPUX86State *env, int next_eip_addend) if (env->hflags & HF_LMA_MASK) { int code64; - ECX = env->eip + next_eip_addend; + env->regs[R_ECX] = env->eip + next_eip_addend; env->regs[11] = cpu_compute_eflags(env); code64 = env->hflags & HF_CS64_MASK; @@ -974,7 +974,7 @@ void helper_syscall(CPUX86State *env, int next_eip_addend) env->eip = env->cstar; } } else { - ECX = (uint32_t)(env->eip + next_eip_addend); + env->regs[R_ECX] = (uint32_t)(env->eip + next_eip_addend); cpu_x86_set_cpl(env, 0); cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc, @@ -1015,14 +1015,14 @@ void helper_sysret(CPUX86State *env, int dflag) DESC_S_MASK | (3 << DESC_DPL_SHIFT) | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | DESC_L_MASK); - env->eip = ECX; + env->eip = env->regs[R_ECX]; } else { cpu_x86_load_seg_cache(env, R_CS, selector | 3, 0, 0xffffffff, DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | (3 << DESC_DPL_SHIFT) | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); - env->eip = (uint32_t)ECX; + env->eip = (uint32_t)env->regs[R_ECX]; } cpu_x86_load_seg_cache(env, R_SS, selector + 8, 0, 0xffffffff, @@ -1039,7 +1039,7 @@ void helper_sysret(CPUX86State *env, int dflag) DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK | (3 << DESC_DPL_SHIFT) | DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); - env->eip = (uint32_t)ECX; + env->eip = (uint32_t)env->regs[R_ECX]; cpu_x86_load_seg_cache(env, R_SS, selector + 8, 0, 0xffffffff, DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | @@ -2288,7 +2288,7 @@ void helper_sysexit(CPUX86State *env, int dflag) DESC_S_MASK | (3 << DESC_DPL_SHIFT) | DESC_W_MASK | DESC_A_MASK); } - ESP = ECX; + ESP = env->regs[R_ECX]; EIP = EDX; } diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c index 28c78a5..952c728 100644 --- a/target-i386/smm_helper.c +++ b/target-i386/smm_helper.c @@ -83,7 +83,7 @@ void do_smm_enter(CPUX86State *env) stq_phys(sm_state + 0x7ed0, env->efer); stq_phys(sm_state + 0x7ff8, env->regs[R_EAX]); - stq_phys(sm_state + 0x7ff0, ECX); + stq_phys(sm_state + 0x7ff0, env->regs[R_ECX]); stq_phys(sm_state + 0x7fe8, EDX); stq_phys(sm_state + 0x7fe0, env->regs[R_EBX]); stq_phys(sm_state + 0x7fd8, ESP); @@ -115,7 +115,7 @@ void do_smm_enter(CPUX86State *env) stl_phys(sm_state + 0x7fe0, ESP); stl_phys(sm_state + 0x7fdc, env->regs[R_EBX]); stl_phys(sm_state + 0x7fd8, EDX); - stl_phys(sm_state + 0x7fd4, ECX); + stl_phys(sm_state + 0x7fd4, env->regs[R_ECX]); stl_phys(sm_state + 0x7fd0, env->regs[R_EAX]); stl_phys(sm_state + 0x7fcc, env->dr[6]); stl_phys(sm_state + 0x7fc8, env->dr[7]); @@ -214,7 +214,7 @@ void helper_rsm(CPUX86State *env) env->tr.flags = (lduw_phys(sm_state + 0x7e92) & 0xf0ff) << 8; env->regs[R_EAX] = ldq_phys(sm_state + 0x7ff8); - ECX = ldq_phys(sm_state + 0x7ff0); + env->regs[R_ECX] = ldq_phys(sm_state + 0x7ff0); EDX = ldq_phys(sm_state + 0x7fe8); env->regs[R_EBX] = ldq_phys(sm_state + 0x7fe0); ESP = ldq_phys(sm_state + 0x7fd8); @@ -250,7 +250,7 @@ void helper_rsm(CPUX86State *env) ESP = ldl_phys(sm_state + 0x7fe0); env->regs[R_EBX] = ldl_phys(sm_state + 0x7fdc); EDX = ldl_phys(sm_state + 0x7fd8); - ECX = ldl_phys(sm_state + 0x7fd4); + env->regs[R_ECX] = ldl_phys(sm_state + 0x7fd4); env->regs[R_EAX] = ldl_phys(sm_state + 0x7fd0); env->dr[6] = ldl_phys(sm_state + 0x7fcc); env->dr[7] = ldl_phys(sm_state + 0x7fc8); diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c index 1243207..b59a2ca 100644 --- a/target-i386/svm_helper.c +++ b/target-i386/svm_helper.c @@ -489,18 +489,18 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type, control.msrpm_base_pa)); uint32_t t0, t1; - switch ((uint32_t)ECX) { + switch ((uint32_t)env->regs[R_ECX]) { case 0 ... 0x1fff: - t0 = (ECX * 2) % 8; - t1 = (ECX * 2) / 8; + t0 = (env->regs[R_ECX] * 2) % 8; + t1 = (env->regs[R_ECX] * 2) / 8; break; case 0xc0000000 ... 0xc0001fff: - t0 = (8192 + ECX - 0xc0000000) * 2; + t0 = (8192 + env->regs[R_ECX] - 0xc0000000) * 2; t1 = (t0 / 8); t0 %= 8; break; case 0xc0010000 ... 0xc0011fff: - t0 = (16384 + ECX - 0xc0010000) * 2; + t0 = (16384 + env->regs[R_ECX] - 0xc0010000) * 2; t1 = (t0 / 8); t0 %= 8; break;