From patchwork Sat Apr 20 18:56:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 238177 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 367A42C0133 for ; Sun, 21 Apr 2013 04:57:30 +1000 (EST) Received: from localhost ([::1]:56684 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UTcyW-0005i6-G6 for incoming@patchwork.ozlabs.org; Sat, 20 Apr 2013 14:57:28 -0400 Received: from eggs.gnu.org ([208.118.235.92]:52537) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UTcxx-0005bC-5y for qemu-devel@nongnu.org; Sat, 20 Apr 2013 14:56:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UTcxv-0007ht-88 for qemu-devel@nongnu.org; Sat, 20 Apr 2013 14:56:53 -0400 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:50114) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UTcxu-0007fg-V5; Sat, 20 Apr 2013 14:56:51 -0400 Received: from [2001:470:d4ed:0:ea11:32ff:fea1:831a] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1UTcxk-0000FA-Ks; Sat, 20 Apr 2013 20:56:40 +0200 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1UTcxi-0007cI-Nu; Sat, 20 Apr 2013 20:56:38 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sat, 20 Apr 2013 20:56:19 +0200 Message-Id: <1366484182-29187-8-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1366484182-29187-1-git-send-email-aurelien@aurel32.net> References: <1366484182-29187-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:470:1f15:c4f::1 Cc: qemu-ppc@nongnu.org, Alexander Graf , Aurelien Jarno Subject: [Qemu-devel] [PATCH v2 07/10] target-ppc: emulate lfiwax instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Needed for Power ISA version 2.05 compliance. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-ppc/translate.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 4b1896f..8298e1f 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2526,7 +2526,6 @@ static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2) } } -#if defined(TARGET_PPC64) static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) { if (unlikely(ctx->le_mode)) { @@ -2536,7 +2535,6 @@ static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2) } else tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx); } -#endif static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2) { @@ -3295,6 +3293,21 @@ GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT); /* lfs lfsu lfsux lfsx */ GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT); +/* lfiwax */ +static void gen_lfiwax(DisasContext *ctx) +{ + TCGv EA; + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + gen_set_access_type(ctx, ACCESS_FLOAT); + EA = tcg_temp_new(); + gen_addr_reg_index(ctx, EA); + gen_qemu_ld32s(ctx, cpu_fpr[rD(ctx->opcode)], EA); + tcg_temp_free(EA); +} + /*** Floating-point store ***/ #define GEN_STF(name, stop, opc, type) \ static void glue(gen_, name)(DisasContext *ctx) \ @@ -9009,6 +9022,7 @@ GEN_LDXF(name, ldop, 0x17, op | 0x00, type) GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT) GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT) +GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205), #undef GEN_STF #undef GEN_STUF