From patchwork Sat Apr 20 18:56:18 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 238180 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A3AAF2C0142 for ; Sun, 21 Apr 2013 04:58:55 +1000 (EST) Received: from localhost ([::1]:32815 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UTczt-00087v-Tc for incoming@patchwork.ozlabs.org; Sat, 20 Apr 2013 14:58:53 -0400 Received: from eggs.gnu.org ([208.118.235.92]:52540) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UTcxx-0005bE-7d for qemu-devel@nongnu.org; Sat, 20 Apr 2013 14:56:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UTcxv-0007hr-8N for qemu-devel@nongnu.org; Sat, 20 Apr 2013 14:56:53 -0400 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:50119) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UTcxu-0007fm-Uy; Sat, 20 Apr 2013 14:56:51 -0400 Received: from [2001:470:d4ed:0:ea11:32ff:fea1:831a] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1UTcxk-0000F9-KZ; Sat, 20 Apr 2013 20:56:40 +0200 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1UTcxi-0007cD-N5; Sat, 20 Apr 2013 20:56:38 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sat, 20 Apr 2013 20:56:18 +0200 Message-Id: <1366484182-29187-7-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1366484182-29187-1-git-send-email-aurelien@aurel32.net> References: <1366484182-29187-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:470:1f15:c4f::1 Cc: qemu-ppc@nongnu.org, Alexander Graf , Aurelien Jarno Subject: [Qemu-devel] [PATCH v2 06/10] target-ppc: emulate fcpsgn instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Needed for Power ISA version 2.05 compliance. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-ppc/translate.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 977f9ef..4b1896f 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -2253,6 +2253,19 @@ static void gen_fneg(DisasContext *ctx) gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); } +/* fcpsgn: PowerPC 2.05 specification */ +/* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */ +static void gen_fcpsgn(DisasContext *ctx) +{ + if (unlikely(!ctx->fpu_enabled)) { + gen_exception(ctx, POWERPC_EXCP_FPU); + return; + } + tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)], + cpu_fpr[rB(ctx->opcode)], 0, 63); + gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); +} + /*** Floating-Point status & ctrl register ***/ /* mcrfs */ @@ -8554,6 +8567,7 @@ GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT), GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT), GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT), GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT), +GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205), GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT), GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT), GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),