From patchwork Sun Mar 24 00:52:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 230361 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id AF1602C00B9 for ; Sun, 24 Mar 2013 11:52:49 +1100 (EST) Received: from localhost ([::1]:42821 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UJZB1-0000zP-VD for incoming@patchwork.ozlabs.org; Sat, 23 Mar 2013 20:52:47 -0400 Received: from eggs.gnu.org ([208.118.235.92]:42008) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UJZAn-0000z9-4e for qemu-devel@nongnu.org; Sat, 23 Mar 2013 20:52:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UJZAm-0007IC-2n for qemu-devel@nongnu.org; Sat, 23 Mar 2013 20:52:33 -0400 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:33767) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UJZAl-0007Hr-Sv for qemu-devel@nongnu.org; Sat, 23 Mar 2013 20:52:32 -0400 Received: from [2001:470:d4ed:0:ea11:32ff:fea1:831a] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1UJZAk-0004o0-BR; Sun, 24 Mar 2013 01:52:30 +0100 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1UJZAj-0005Qf-6x; Sun, 24 Mar 2013 01:52:29 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sun, 24 Mar 2013 01:52:26 +0100 Message-Id: <1364086346-20819-1-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:470:1f15:c4f::1 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH] tcg-mips: Implement muls2_i32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson --- tcg/mips/tcg-target.c | 6 ++++++ tcg/mips/tcg-target.h | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index bd8c858..373c364 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -1413,6 +1413,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0); #endif break; + case INDEX_op_muls2_i32: + tcg_out_opc_reg(s, OPC_MULT, 0, args[2], args[3]); + tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0); + tcg_out_opc_reg(s, OPC_MFHI, args[1], 0, 0); + break; case INDEX_op_mulu2_i32: tcg_out_opc_reg(s, OPC_MULTU, 0, args[2], args[3]); tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0); @@ -1595,6 +1600,7 @@ static const TCGTargetOpDef mips_op_defs[] = { { INDEX_op_add_i32, { "r", "rZ", "rJ" } }, { INDEX_op_mul_i32, { "r", "rZ", "rZ" } }, + { INDEX_op_muls2_i32, { "r", "r", "rZ", "rZ" } }, { INDEX_op_mulu2_i32, { "r", "r", "rZ", "rZ" } }, { INDEX_op_div_i32, { "r", "rZ", "rZ" } }, { INDEX_op_divu_i32, { "r", "rZ", "rZ" } }, diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 0384bd3..6155327 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -87,7 +87,7 @@ typedef enum { #define TCG_TARGET_HAS_orc_i32 0 #define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_nand_i32 0 -#define TCG_TARGET_HAS_muls2_i32 0 +#define TCG_TARGET_HAS_muls2_i32 1 /* optional instructions only implemented on MIPS4, MIPS32 and Loongson 2 */ #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \