From patchwork Wed Nov 14 14:38:21 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 198922 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4D9152C030E for ; Thu, 15 Nov 2012 01:38:58 +1100 (EST) Received: from localhost ([::1]:35671 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TYe7D-0001oF-Hf for incoming@patchwork.ozlabs.org; Wed, 14 Nov 2012 09:38:55 -0500 Received: from eggs.gnu.org ([208.118.235.92]:56226) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TYe74-0001nS-NU for qemu-devel@nongnu.org; Wed, 14 Nov 2012 09:38:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TYe71-0000Ly-Ld for qemu-devel@nongnu.org; Wed, 14 Nov 2012 09:38:46 -0500 Received: from hall.aurel32.net ([2001:470:1f15:c4f::1]:53226) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TYe71-0000Km-Eo for qemu-devel@nongnu.org; Wed, 14 Nov 2012 09:38:43 -0500 Received: from wifi-pers-0465.univ-lyon1.fr ([134.214.213.210] helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TYe6r-0005if-LW; Wed, 14 Nov 2012 15:38:33 +0100 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TYe6m-0002IR-4J; Wed, 14 Nov 2012 15:38:28 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Wed, 14 Nov 2012 15:38:21 +0100 Message-Id: <1352903901-8797-1-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:470:1f15:c4f::1 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH] mips/malta: fix CBUS UART interrupt pin X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org According to the MIPS Malta Developement Platform User's Manual, the i8259 interrupt controller is supposed to be connected to the hardware IRQ0, and the CBUS UART to the hardware interrupt 2. In QEMU they are both connected to hardware interrupt 0, the CBUS UART interrupt being wrong. This patch fixes that. It should be noted that the irq array in QEMU includes the software interrupts, hence env->irq[2] is the first hardware interrupt. Cc: Ralf Baechle Signed-off-by: Aurelien Jarno Reviewed-by: Eric Johnson --- hw/mips_malta.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/mips_malta.c b/hw/mips_malta.c index 0571d58..4d2464a 100644 --- a/hw/mips_malta.c +++ b/hw/mips_malta.c @@ -861,7 +861,8 @@ void mips_malta_init(QEMUMachineInitArgs *args) be = 0; #endif /* FPGA */ - malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[2], serial_hds[2]); + /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */ + malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[4], serial_hds[2]); /* Load firmware in flash / BIOS. */ dinfo = drive_get(IF_PFLASH, 0, fl_idx);