From patchwork Tue Oct 30 00:11:55 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 195176 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D44D22C0084 for ; Tue, 30 Oct 2012 11:12:42 +1100 (EST) Received: from localhost ([::1]:59131 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TSzRg-0007Ch-Rm for incoming@patchwork.ozlabs.org; Mon, 29 Oct 2012 20:12:40 -0400 Received: from eggs.gnu.org ([208.118.235.92]:43506) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TSzRN-00078S-3C for qemu-devel@nongnu.org; Mon, 29 Oct 2012 20:12:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TSzRL-0005AI-Kn for qemu-devel@nongnu.org; Mon, 29 Oct 2012 20:12:21 -0400 Received: from hall.aurel32.net ([88.191.126.93]:39626) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TSzRL-00059V-0b for qemu-devel@nongnu.org; Mon, 29 Oct 2012 20:12:19 -0400 Received: from 89-92-80-242.hfc.dyn.abo.bbox.fr ([89.92.80.242] helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TSzRJ-0000QW-4L; Tue, 30 Oct 2012 01:12:17 +0100 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TSzRF-0005BY-Tf; Tue, 30 Oct 2012 01:12:13 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Tue, 30 Oct 2012 01:11:55 +0100 Message-Id: <1351555932-19695-3-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1351555932-19695-1-git-send-email-aurelien@aurel32.net> References: <1351555932-19695-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 88.191.126.93 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH v2 02/19] target-mips: do not save CPU state when using retranslation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org When the CPU state after a possible retranslation is going to be handled through code retranslation, we don't need to save the CPU state before. Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 3cf4ca1..97a63ea 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1171,13 +1171,11 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, switch (opc) { #if defined(TARGET_MIPS64) case OPC_LWU: - save_cpu_state(ctx, 0); op_ld_lwu(t0, t0, ctx); gen_store_gpr(t0, rt); opn = "lwu"; break; case OPC_LD: - save_cpu_state(ctx, 0); op_ld_ld(t0, t0, ctx); gen_store_gpr(t0, rt); opn = "ld"; @@ -1203,7 +1201,6 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, opn = "ldr"; break; case OPC_LDPC: - save_cpu_state(ctx, 0); tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); op_ld_ld(t0, t0, ctx); @@ -1212,7 +1209,6 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, break; #endif case OPC_LWPC: - save_cpu_state(ctx, 0); tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); op_ld_lw(t0, t0, ctx); @@ -1220,31 +1216,26 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, opn = "lwpc"; break; case OPC_LW: - save_cpu_state(ctx, 0); op_ld_lw(t0, t0, ctx); gen_store_gpr(t0, rt); opn = "lw"; break; case OPC_LH: - save_cpu_state(ctx, 0); op_ld_lh(t0, t0, ctx); gen_store_gpr(t0, rt); opn = "lh"; break; case OPC_LHU: - save_cpu_state(ctx, 0); op_ld_lhu(t0, t0, ctx); gen_store_gpr(t0, rt); opn = "lhu"; break; case OPC_LB: - save_cpu_state(ctx, 0); op_ld_lb(t0, t0, ctx); gen_store_gpr(t0, rt); opn = "lb"; break; case OPC_LBU: - save_cpu_state(ctx, 0); op_ld_lbu(t0, t0, ctx); gen_store_gpr(t0, rt); opn = "lbu"; @@ -1289,7 +1280,6 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt, switch (opc) { #if defined(TARGET_MIPS64) case OPC_SD: - save_cpu_state(ctx, 0); op_st_sd(t1, t0, ctx); opn = "sd"; break; @@ -1305,17 +1295,14 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt, break; #endif case OPC_SW: - save_cpu_state(ctx, 0); op_st_sw(t1, t0, ctx); opn = "sw"; break; case OPC_SH: - save_cpu_state(ctx, 0); op_st_sh(t1, t0, ctx); opn = "sh"; break; case OPC_SB: - save_cpu_state(ctx, 0); op_st_sb(t1, t0, ctx); opn = "sb"; break; @@ -8149,7 +8136,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, } /* Don't do NOP if destination is zero: we must perform the actual memory access. */ - save_cpu_state(ctx, 0); switch (opc) { case OPC_LWXC1: check_cop1x(ctx); @@ -10422,7 +10408,6 @@ static void gen_ldxs (DisasContext *ctx, int base, int index, int rd) gen_op_addr_add(ctx, t0, t1, t0); } - save_cpu_state(ctx, 0); op_ld_lw(t1, t0, ctx); gen_store_gpr(t1, rd); @@ -10452,7 +10437,6 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, generate_exception(ctx, EXCP_RI); return; } - save_cpu_state(ctx, 0); op_ld_lw(t1, t0, ctx); gen_store_gpr(t1, rd); tcg_gen_movi_tl(t1, 4); @@ -10462,7 +10446,6 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, opn = "lwp"; break; case SWP: - save_cpu_state(ctx, 0); gen_load_gpr(t1, rd); op_st_sw(t1, t0, ctx); tcg_gen_movi_tl(t1, 4); @@ -10477,7 +10460,6 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, generate_exception(ctx, EXCP_RI); return; } - save_cpu_state(ctx, 0); op_ld_ld(t1, t0, ctx); gen_store_gpr(t1, rd); tcg_gen_movi_tl(t1, 8); @@ -10487,7 +10469,6 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, opn = "ldp"; break; case SDP: - save_cpu_state(ctx, 0); gen_load_gpr(t1, rd); op_st_sd(t1, t0, ctx); tcg_gen_movi_tl(t1, 8);