From patchwork Fri Oct 19 21:25:50 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 192824 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id DDB6F2C0096 for ; Sat, 20 Oct 2012 08:26:09 +1100 (EST) Received: from localhost ([::1]:46500 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TPK52-0001K9-0v for incoming@patchwork.ozlabs.org; Fri, 19 Oct 2012 17:26:08 -0400 Received: from eggs.gnu.org ([208.118.235.92]:40989) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TPK4v-0001JR-Pn for qemu-devel@nongnu.org; Fri, 19 Oct 2012 17:26:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TPK4u-00013n-Ix for qemu-devel@nongnu.org; Fri, 19 Oct 2012 17:26:01 -0400 Received: from hall.aurel32.net ([88.191.126.93]:41785) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TPK4u-00013h-Cm for qemu-devel@nongnu.org; Fri, 19 Oct 2012 17:26:00 -0400 Received: from watt.aurel32.net ([82.228.202.134] helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TPK4s-0004It-IT; Fri, 19 Oct 2012 23:25:58 +0200 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TPK4r-0007xN-Uu; Fri, 19 Oct 2012 23:25:57 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Fri, 19 Oct 2012 23:25:50 +0200 Message-Id: <1350681950-30547-1-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 88.191.126.93 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH] tcg/mips: use MUL instead of MULT on MIPS32 and above X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org MIPS32 and later instruction sets have a multiplication instruction directly operating on GPRs. It only produces a 32-bit result but it is exactly what is needed by QEMU. Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson --- tcg/mips/tcg-target.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index 7e4013e..ae2b274 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -323,6 +323,9 @@ enum { OPC_BLTZ = OPC_REGIMM | (0x00 << 16), OPC_BGEZ = OPC_REGIMM | (0x01 << 16), + OPC_SPECIAL2 = 0x1c << 26, + OPC_MUL = OPC_SPECIAL2 | 0x002, + OPC_SPECIAL3 = 0x1f << 26, OPC_INS = OPC_SPECIAL3 | 0x004, OPC_WSBH = OPC_SPECIAL3 | 0x0a0, @@ -1403,8 +1406,12 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_mov(s, TCG_TYPE_I32, args[0], TCG_REG_AT); break; case INDEX_op_mul_i32: +#if defined(__mips_isa_rev) && (__mips_isa_rev >= 1) + tcg_out_opc_reg(s, OPC_MUL, args[0], args[1], args[2]); +#else tcg_out_opc_reg(s, OPC_MULT, 0, args[1], args[2]); tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0); +#endif break; case INDEX_op_mulu2_i32: tcg_out_opc_reg(s, OPC_MULTU, 0, args[2], args[3]);