From patchwork Tue Oct 16 23:28:35 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 191912 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9F39B2C0098 for ; Wed, 17 Oct 2012 10:28:55 +1100 (EST) Received: from localhost ([::1]:55575 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TOGZB-0006bw-IF for incoming@patchwork.ozlabs.org; Tue, 16 Oct 2012 19:28:53 -0400 Received: from eggs.gnu.org ([208.118.235.92]:42395) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TOGZ1-0006bX-6P for qemu-devel@nongnu.org; Tue, 16 Oct 2012 19:28:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TOGZ0-0006IH-3Y for qemu-devel@nongnu.org; Tue, 16 Oct 2012 19:28:43 -0400 Received: from hall.aurel32.net ([88.191.126.93]:52906) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TOGYz-0006I9-Tw for qemu-devel@nongnu.org; Tue, 16 Oct 2012 19:28:42 -0400 Received: from [2001:470:d4ed:1:2db:dfff:fe14:52d] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TOGYz-0004Jd-1W; Wed, 17 Oct 2012 01:28:41 +0200 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TOGYx-0006BK-5H; Wed, 17 Oct 2012 01:28:39 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Wed, 17 Oct 2012 01:28:35 +0200 Message-Id: <1350430115-23724-2-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1350430115-23724-1-git-send-email-aurelien@aurel32.net> References: <1350430115-23724-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 88.191.126.93 Cc: Blue Swirl , Aurelien Jarno Subject: [Qemu-devel] [PATCH 2/2] target-sparc: fix FMOVr instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Like the MOVr instruction, the FMOVr instruction has the condition encoded between bits 10 and 12. Cc: Blue Swirl Signed-off-by: Aurelien Jarno --- target-sparc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 6cef96b..6d05e7d 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -3154,7 +3154,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) #define FMOVR(sz) \ do { \ DisasCompare cmp; \ - cond = GET_FIELD_SP(insn, 14, 17); \ + cond = GET_FIELD_SP(insn, 10, 12); \ cpu_src1 = get_src1(insn, cpu_src1); \ gen_compare_reg(&cmp, cond, cpu_src1); \ gen_fmov##sz(dc, &cmp, rd, rs2); \