From patchwork Tue Oct 9 20:30:50 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 190473 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 4E2302C00A9 for ; Wed, 10 Oct 2012 08:51:07 +1100 (EST) Received: from localhost ([::1]:53940 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgSn-00056z-S3 for incoming@patchwork.ozlabs.org; Tue, 09 Oct 2012 16:31:37 -0400 Received: from eggs.gnu.org ([208.118.235.92]:50572) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgSB-0003Ma-7h for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:31:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TLgS8-0006EP-Q7 for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:30:59 -0400 Received: from hall.aurel32.net ([88.191.126.93]:42140) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgS8-0006Dr-Kh; Tue, 09 Oct 2012 16:30:56 -0400 Received: from [2001:470:d4ed:0:ea11:32ff:fea1:831a] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TLgS7-00079w-IF; Tue, 09 Oct 2012 22:30:55 +0200 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TLgS5-0005p2-Jm; Tue, 09 Oct 2012 22:30:53 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Tue, 9 Oct 2012 22:30:50 +0200 Message-Id: <1349814652-22325-4-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1349814652-22325-1-git-send-email-aurelien@aurel32.net> References: <1349814652-22325-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 88.191.126.93 Cc: Jia Liu , Aurelien Jarno , qemu-stable@nongnu.org Subject: [Qemu-devel] [PATCH 3/5] target-openrisc: remove conflicting definitions from cpu.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org On an ARM host, the registers definitions from cpu.h clash with /usr/include/sys/ucontext.h. As there are unused, just remove them. Cc: Jia Liu Cc: qemu-stable@nongnu.org Signed-off-by: Aurelien Jarno --- target-openrisc/cpu.h | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index de21a87..244788c 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -89,24 +89,6 @@ enum { /* Interrupt */ #define NR_IRQS 32 -/* Registers */ -enum { - R0 = 0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, - R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, - R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, - R31 -}; - -/* Register aliases */ -enum { - R_ZERO = R0, - R_SP = R1, - R_FP = R2, - R_LR = R9, - R_RV = R11, - R_RVH = R12 -}; - /* Unit presece register */ enum { UPR_UP = (1 << 0),