From patchwork Fri Oct 5 00:08:57 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peter A. G. Crosthwaite" X-Patchwork-Id: 189377 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 520EE2C0091 for ; Fri, 5 Oct 2012 10:31:12 +1000 (EST) Received: from localhost ([::1]:58452 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJvos-0000kw-Fq for incoming@patchwork.ozlabs.org; Thu, 04 Oct 2012 20:31:10 -0400 Received: from eggs.gnu.org ([208.118.235.92]:52337) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJvUb-0004qI-PK for qemu-devel@nongnu.org; Thu, 04 Oct 2012 20:10:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TJvUX-0002MI-PT for qemu-devel@nongnu.org; Thu, 04 Oct 2012 20:10:13 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:50471) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJvUX-0001eJ-ID for qemu-devel@nongnu.org; Thu, 04 Oct 2012 20:10:09 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp2so1103615pbb.4 for ; Thu, 04 Oct 2012 17:10:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=dZNzt43Iuz00m21ecmdvIrL3qbVQKoAAPNYl1Rqizcc=; b=Ciy7A4Iw7TjY9F9F3+FI/h6W2zU+fM3oNhtT34bXfkUOmPSlOPn5afAJusr1/FYkxe TXuAA4OCJTTHwdLX8VvIqNbxfTKfNp6h+/wVNPLsJPErftvN7ZRH1vJe69ur408vPCAs ChYKOLQPddGCh4Pwe2K8PwQPzXNj8ABjgGCnqohvgUxKX5wBZKTPQ6ZD3660oTvcg1hT i9GzMBdF+HGWGIlDX3VF1KqBlRwYR/dDZs1HQ+ZFp9UiT+4TZVfWN5IqL1trcyrxjSAZ 7L3CLrASpSnvB491iiCFvBd1m0Pa3xgkV8dfU1ServzdkR4n3/3FNxhdDkwc2x3Tfm5b ixwg== Received: by 10.68.242.164 with SMTP id wr4mr26253118pbc.41.1349395807172; Thu, 04 Oct 2012 17:10:07 -0700 (PDT) Received: from localhost ([124.148.20.9]) by mx.google.com with ESMTPS id st6sm5069959pbc.58.2012.10.04.17.10.04 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 04 Oct 2012 17:10:06 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org, edgar.iglesias@gmail.com, blauwirbel@gmail.com, aliguori@us.ibm.com Date: Fri, 5 Oct 2012 10:08:57 +1000 Message-Id: <1349395739-26502-13-git-send-email-peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1349395739-26502-1-git-send-email-peter.crosthwaite@xilinx.com> References: <1349395739-26502-1-git-send-email-peter.crosthwaite@xilinx.com> X-Gm-Message-State: ALoCoQmvcfG/iv/WIG2jbkJHHE8zv4xAh+Gk6iVloT3qHlLjZO/XLJR8eA+QnmHKoD45V745kdig X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: peter.crosthwaite@petalogix.com Subject: [Qemu-devel] [PATCH 12/14] xilinx_zynq: Added SPI controllers + flashes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter A. G. Crosthwaite Added the two SPI controllers to the zynq machine model. Attached two SPI flash devices to each controller. Signed-off-by: Peter A. G. Crosthwaite --- hw/xilinx_zynq.c | 34 ++++++++++++++++++++++++++++++++++ 1 files changed, 34 insertions(+), 0 deletions(-) diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c index 7e6c273..fd46ba2 100644 --- a/hw/xilinx_zynq.c +++ b/hw/xilinx_zynq.c @@ -24,6 +24,9 @@ #include "flash.h" #include "blockdev.h" #include "loader.h" +#include "ssi.h" + +#define NUM_SPI_FLASHES 4 #define FLASH_SIZE (64 * 1024 * 1024) #define FLASH_SECTOR_SIZE (128 * 1024) @@ -46,6 +49,34 @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) sysbus_connect_irq(s, 0, irq); } +static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq) +{ + DeviceState *dev; + SysBusDevice *busdev; + SSIBus *spi; + int i; + + dev = qdev_create(NULL, "xilinx,spips"); + qdev_init_nofail(dev); + busdev = sysbus_from_qdev(dev); + sysbus_mmio_map(busdev, 0, base_addr); + sysbus_connect_irq(busdev, 0, irq); + + spi = (SSIBus *)qdev_get_child_bus(dev, "spi"); + + for (i = 0; i < NUM_SPI_FLASHES; ++i) { + qemu_irq cs_line; + + dev = ssi_create_slave_no_init(spi, "m25p80"); + qdev_prop_set_string(dev, "partname", "n25q128"); + qdev_init_nofail(dev); + + cs_line = qdev_get_gpio_in(dev, 0); + sysbus_connect_irq(busdev, i+1, cs_line); + } + +} + static void zynq_init(ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -113,6 +144,9 @@ static void zynq_init(ram_addr_t ram_size, const char *boot_device, pic[n] = qdev_get_gpio_in(dev, n); } + zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET]); + zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET]); + sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]); sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);