From patchwork Fri Oct 5 00:08:55 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peter A. G. Crosthwaite" X-Patchwork-Id: 189384 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id F324F2C00B9 for ; Fri, 5 Oct 2012 10:51:02 +1000 (EST) Received: from localhost ([::1]:52097 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJvUZ-0004cG-1N for incoming@patchwork.ozlabs.org; Thu, 04 Oct 2012 20:10:11 -0400 Received: from eggs.gnu.org ([208.118.235.92]:52288) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJvUK-0004Kr-UC for qemu-devel@nongnu.org; Thu, 04 Oct 2012 20:09:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TJvUJ-00027M-Up for qemu-devel@nongnu.org; Thu, 04 Oct 2012 20:09:56 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:50471) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJvUJ-0001eJ-OK for qemu-devel@nongnu.org; Thu, 04 Oct 2012 20:09:55 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp2so1103615pbb.4 for ; Thu, 04 Oct 2012 17:09:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=NVHuVCl2Jg315ojGbvyz3N+GknkaKKI8BxzfeuKRL1Y=; b=SFvOJQnZaiiwZw4DOk8ebh+pO+/cEj/idK98pBXOdjdJR4OFs91r+9aBXpSu3foY6L VnSpEPVmSHJzV4/jI3UbQqteeanihQvdZrXhTpWP7dw0kQOFTnDHPrL7PTMliSXJq/ol Ttmvf9kY6X67mHEavjHwIj1qLqgr4y5Bjpi7l+vegMp+pqNejlu7yrnRnKWiMHyfGjyV RMmHK/0mDEiH+5xGCwFuHTyGaUueCrsivzwibhwJFxb/VZEslyTXRhMQMxYZfqgDGOAs 88ajqDk5SY6Bj/c4s3kuShnnV/RpxKcFVqa2LbMazyeNczSY4coG1TQiLYs6oJYBUxlq B7jw== Received: by 10.68.136.100 with SMTP id pz4mr954405pbb.135.1349395795464; Thu, 04 Oct 2012 17:09:55 -0700 (PDT) Received: from localhost ([124.148.20.9]) by mx.google.com with ESMTPS id pw2sm3422461pbb.59.2012.10.04.17.09.52 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 04 Oct 2012 17:09:54 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org, edgar.iglesias@gmail.com, blauwirbel@gmail.com, aliguori@us.ibm.com Date: Fri, 5 Oct 2012 10:08:55 +1000 Message-Id: <1349395739-26502-11-git-send-email-peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1349395739-26502-1-git-send-email-peter.crosthwaite@xilinx.com> References: <1349395739-26502-1-git-send-email-peter.crosthwaite@xilinx.com> X-Gm-Message-State: ALoCoQkxYk7/RtbRlrRm51Ts5TpqhqqB2yZ2lvt/4wPIkMb88r66w186sUkekCKirDUa1Iq3SLTm X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: peter.crosthwaite@petalogix.com Subject: [Qemu-devel] [PATCH 10/14] petalogix-ml605: added SPI controller with n25q128 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter A. G. Crosthwaite Added SPI controller to the reference design, with two n25q128 spi-flashes connected. Signed-off-by: Peter A. G. Crosthwaite --- hw/petalogix_ml605_mmu.c | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-) diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c index dced648..b9bfbed 100644 --- a/hw/petalogix_ml605_mmu.c +++ b/hw/petalogix_ml605_mmu.c @@ -36,6 +36,7 @@ #include "blockdev.h" #include "pc.h" #include "exec-memory.h" +#include "ssi.h" #include "microblaze_boot.h" #include "microblaze_pic_cpu.h" @@ -47,6 +48,8 @@ #define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb" +#define NUM_SPI_FLASHES 4 + #define MEMORY_BASEADDR 0x50000000 #define FLASH_BASEADDR 0x86000000 #define INTC_BASEADDR 0x81800000 @@ -79,6 +82,7 @@ petalogix_ml605_init(ram_addr_t ram_size, MemoryRegion *address_space_mem = get_system_memory(); DeviceState *dev, *dma, *eth0; MicroBlazeCPU *cpu; + SysBusDevice *busdev; CPUMBState *env; DriveInfo *dinfo; int i; @@ -139,6 +143,29 @@ petalogix_ml605_init(ram_addr_t ram_size, xilinx_axiethernetdma_init(dma, STREAM_SLAVE(eth0), 0x84600000, irq[1], irq[0], 100 * 1000000); + { + SSIBus *spi; + + dev = qdev_create(NULL, "xlnx.xps-spi"); + qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES); + qdev_init_nofail(dev); + busdev = sysbus_from_qdev(dev); + sysbus_mmio_map(busdev, 0, 0x40a00000); + sysbus_connect_irq(busdev, 0, irq[4]); + + spi = (SSIBus *)qdev_get_child_bus(dev, "spi"); + + for (i = 0; i < NUM_SPI_FLASHES; i++) { + qemu_irq cs_line; + + dev = ssi_create_slave_no_init(spi, "m25p80"); + qdev_prop_set_string(dev, "partname", "n25q128"); + qdev_init_nofail(dev); + cs_line = qdev_get_gpio_in(dev, 0); + sysbus_connect_irq(busdev, i+1, cs_line); + } + } + microblaze_load_kernel(cpu, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE, machine_cpu_reset);