From patchwork Thu Sep 27 22:40:02 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187498 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8A1CB2C0085 for ; Fri, 28 Sep 2012 08:42:55 +1000 (EST) Received: from localhost ([::1]:43408 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THMnF-0006p7-Po for incoming@patchwork.ozlabs.org; Thu, 27 Sep 2012 18:42:53 -0400 Received: from eggs.gnu.org ([208.118.235.92]:36072) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THMl8-00042P-JQ for qemu-devel@nongnu.org; Thu, 27 Sep 2012 18:40:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1THMl6-0003Iz-Rq for qemu-devel@nongnu.org; Thu, 27 Sep 2012 18:40:42 -0400 Received: from mail-pa0-f45.google.com ([209.85.220.45]:37069) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THMl6-00031E-Je for qemu-devel@nongnu.org; Thu, 27 Sep 2012 18:40:40 -0400 Received: by mail-pa0-f45.google.com with SMTP id fb10so1737833pad.4 for ; Thu, 27 Sep 2012 15:40:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=PkxRCr0MfFPd9p3GWdvBlxEHEOVzyhXAjOQ7UI0Fd9w=; b=cBpdXKVfUsCfJ6Cvvg1hOYEOFg8F6WnoN6T4LTwYnL73cNrDJqE3v4Nsr/5a1t1Hgk i45f6HyNh4p6KaTeP9Fku2znM7oFU7eA4o2kOJmeCaAYfJqekBH+eKeuCGRUBUyvLZ92 soh9nwABDbo6ESf/mFoo7cWHG1eGrz0sINbN+S85dGeuo2mmGoR5sdtutE57u5O2pZAx yKGFGW7eFDb1z752yfOjxf0Q4TyK7OifW6U8NnBknpm1uwOSU+qkHd2xU4MEZLaX9Sco LiTzyu4bbjN1PPe2La2KO0Ys1nB4nspUVsiUA3X6ihiRBp7bg8fEUEM/REYi/778dA3t TGpg== Received: by 10.66.74.201 with SMTP id w9mr12694669pav.74.1348785640152; Thu, 27 Sep 2012 15:40:40 -0700 (PDT) Received: from anchor.twiddle.home.com ([173.160.232.49]) by mx.google.com with ESMTPS id sj5sm4480267pbc.30.2012.09.27.15.40.39 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 27 Sep 2012 15:40:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 Sep 2012 15:40:02 -0700 Message-Id: <1348785610-23418-22-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1348785610-23418-1-git-send-email-rth@twiddle.net> References: <1348785610-23418-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.220.45 Cc: Alexander Graf Subject: [Qemu-devel] [PATCH 021/147] target-s390: Convert 64-bit MULTIPLY LOGICAL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Use a new "retxl" member of CPUS290XState to return the "eXtra Low" part of a 128-bit value. That said, this will get used when two independent values need returning (e.g. quotient+remainder) as well. At the same time, shuffle the elements of CPUS390XState to get this new space from existing padding in the structure. Signed-off-by: Richard Henderson --- target-s390x/cpu.h | 15 +++++++++------ target-s390x/helper.h | 2 +- target-s390x/insn-data.def | 2 ++ target-s390x/int_helper.c | 15 ++++----------- target-s390x/translate.c | 36 ++++++++++++++++++++++++++++-------- 5 files changed, 44 insertions(+), 26 deletions(-) diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h index 2c5a743..453be35 100644 --- a/target-s390x/cpu.h +++ b/target-s390x/cpu.h @@ -60,17 +60,20 @@ typedef struct ExtQueue { } ExtQueue; typedef struct CPUS390XState { - uint64_t regs[16]; /* GP registers */ + uint64_t regs[16]; /* GP registers */ + CPU_DoubleU fregs[16]; /* FP registers */ + uint32_t aregs[16]; /* access registers */ - uint32_t aregs[16]; /* access registers */ + uint32_t fpc; /* floating-point control register */ + uint32_t cc_op; - uint32_t fpc; /* floating-point control register */ - CPU_DoubleU fregs[16]; /* FP registers */ float_status fpu_status; /* passed to softfloat lib */ + /* The low part of a 128-bit return, or remainder of a divide. */ + uint64_t retxl; + PSW psw; - uint32_t cc_op; uint64_t cc_src; uint64_t cc_dst; uint64_t cc_vr; @@ -86,8 +89,8 @@ typedef struct CPUS390XState { uint64_t cregs[16]; /* control registers */ - int pending_int; ExtQueue ext_queue[MAX_EXT_QUEUE]; + int pending_int; int ext_index; diff --git a/target-s390x/helper.h b/target-s390x/helper.h index e72e16e..8527fbb 100644 --- a/target-s390x/helper.h +++ b/target-s390x/helper.h @@ -9,7 +9,7 @@ DEF_HELPER_4(clc, i32, env, i32, i64, i64) DEF_HELPER_3(mvcl, i32, env, i32, i32) DEF_HELPER_4(clm, i32, env, i32, i32, i64) DEF_HELPER_4(stcm, void, env, i32, i32, i64) -DEF_HELPER_3(mlg, void, env, i32, i64) +DEF_HELPER_FLAGS_3(mul128, TCG_CALL_CONST, i64, env, i64, i64) DEF_HELPER_3(dlg, void, env, i32, i64) DEF_HELPER_4(srst, i32, env, i32, i32, i32) DEF_HELPER_4(clst, i32, env, i32, i32, i32) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index ca12e47..94cd220 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -54,6 +54,8 @@ /* MULTIPLY LOGICAL */ C(0xb996, MLR, RRE, Z, r1p1_32u, r2_32u, new, r1_D32, mul, 0) C(0xe396, ML, RXY_a, Z, r1p1_32u, m2_32u, new, r1_D32, mul, 0) + C(0xb986, MLGR, RRE, Z, r1p1, r2_o, r1_P, 0, mul128, 0) + C(0xe386, MLG, RXY_a, Z, r1p1, m2_64, r1_P, 0, mul128, 0) /* MULTIPLY SINGLE */ C(0xb252, MSR, RRE, Z, r1_o, r2_o, new, r1_32, mul, 0) C(0x7100, MS, RX_a, Z, r1_o, m2_32s, new, r1_32, mul, 0) diff --git a/target-s390x/int_helper.c b/target-s390x/int_helper.c index f202a7e..e54faea 100644 --- a/target-s390x/int_helper.c +++ b/target-s390x/int_helper.c @@ -30,18 +30,11 @@ #endif /* 64/64 -> 128 unsigned multiplication */ -void HELPER(mlg)(CPUS390XState *env, uint32_t r1, uint64_t v2) +uint64_t HELPER(mul128)(CPUS390XState *env, uint64_t v1, uint64_t v2) { -#if HOST_LONG_BITS == 64 && defined(__GNUC__) - /* assuming 64-bit hosts have __uint128_t */ - __uint128_t res = (__uint128_t)env->regs[r1 + 1]; - - res *= (__uint128_t)v2; - env->regs[r1] = (uint64_t)(res >> 64); - env->regs[r1 + 1] = (uint64_t)res; -#else - mulu64(&env->regs[r1 + 1], &env->regs[r1], env->regs[r1 + 1], v2); -#endif + uint64_t reth; + mulu64(&env->retxl, &reth, v1, v2); + return reth; } /* 128 -> 64/64 unsigned division */ diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 66e6b60..77305b5 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -293,6 +293,11 @@ static inline void store_freg32(int reg, TCGv_i32 v) #endif } +static inline void return_low128(TCGv_i64 dest) +{ + tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl)); +} + static inline void update_psw_addr(DisasContext *s) { /* psw.addr */ @@ -1563,14 +1568,6 @@ static void disas_e3(CPUS390XState *env, DisasContext* s, int op, int r1, set_cc_nz_u64(s, regs[r1]); tcg_temp_free_i64(tmp3); break; - case 0x86: /* MLG R1,D2(X2,B2) [RXY] */ - tmp2 = tcg_temp_new_i64(); - tmp32_1 = tcg_const_i32(r1); - tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s)); - gen_helper_mlg(cpu_env, tmp32_1, tmp2); - tcg_temp_free_i64(tmp2); - tcg_temp_free_i32(tmp32_1); - break; case 0x87: /* DLG R1,D2(X2,B2) [RXY] */ tmp2 = tcg_temp_new_i64(); tmp32_1 = tcg_const_i32(r1); @@ -4732,6 +4729,13 @@ static ExitStatus op_mul(DisasContext *s, DisasOps *o) return NO_EXIT; } +static ExitStatus op_mul128(DisasContext *s, DisasOps *o) +{ + gen_helper_mul128(o->out, cpu_env, o->in1, o->in2); + return_low128(o->out2); + return NO_EXIT; +} + static ExitStatus op_sub(DisasContext *s, DisasOps *o) { tcg_gen_sub_i64(o->out, o->in1, o->in2); @@ -4800,6 +4804,15 @@ static void prep_r1(DisasContext *s, DisasFields *f, DisasOps *o) o->g_out = true; } +static void prep_r1_P(DisasContext *s, DisasFields *f, DisasOps *o) +{ + /* ??? Specification exception: r1 must be even. */ + int r1 = get_field(f, r1); + o->out = regs[r1]; + o->out2 = regs[(r1 + 1) & 15]; + o->g_out = o->g_out2 = true; +} + /* ====================================================================== */ /* The "Write OUTput" generators. These generally perform some non-trivial copy of data to TCG globals, or to main memory. The trivial cases are @@ -4844,6 +4857,13 @@ static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o) o->g_in1 = true; } +static void in1_r1p1(DisasContext *s, DisasFields *f, DisasOps *o) +{ + /* ??? Specification exception: r1 must be even. */ + int r1 = get_field(f, r1); + o->in1 = load_reg((r1 + 1) & 15); +} + static void in1_r1p1_32s(DisasContext *s, DisasFields *f, DisasOps *o) { /* ??? Specification exception: r1 must be even. */