From patchwork Thu Sep 27 22:40:01 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187496 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 05AC42C00B5 for ; Fri, 28 Sep 2012 08:42:40 +1000 (EST) Received: from localhost ([::1]:42074 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THMn0-00067l-8A for incoming@patchwork.ozlabs.org; Thu, 27 Sep 2012 18:42:38 -0400 Received: from eggs.gnu.org ([208.118.235.92]:36061) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THMl7-0003zu-Rs for qemu-devel@nongnu.org; Thu, 27 Sep 2012 18:40:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1THMl5-0003Hj-Me for qemu-devel@nongnu.org; Thu, 27 Sep 2012 18:40:41 -0400 Received: from mail-pa0-f45.google.com ([209.85.220.45]:37069) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1THMl5-00031E-Gc for qemu-devel@nongnu.org; Thu, 27 Sep 2012 18:40:39 -0400 Received: by mail-pa0-f45.google.com with SMTP id fb10so1737833pad.4 for ; Thu, 27 Sep 2012 15:40:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=IKrxvzq5NBcsQELLjy0zhpu7qReaFpSaGy1Dq1eZWJc=; b=TnbsxIFmJ6ey4c/RX1i9pqNeZ3t3LAVlCm7DJEk+r3ABnniV1ZxRsNacDrxkTL/2Rm JruM7cNuS06SN7oRBx7oQkZuBJecff6SH/alnWKhGE9xH3vMkCoMnSF1k9CwBmyDJwY4 l1fKYYDiyywlLSF7a11q+iEty0p+/nrQ6g1fWKe//3OUPsfeVuE5eVnvMhCY33oUuzts PENDti/48s4794yba99ad0JNh81D6UXA13A2GVJAWL+4C70ors1IaOlPJg3HTZGJu8e0 kgvTucGib7qncajlBecYOGwL/acuAHcGV90XKioC3bKPEvyxdLD4dxkej8ucGVOn8w0r HxoA== Received: by 10.68.221.166 with SMTP id qf6mr15345353pbc.54.1348785639093; Thu, 27 Sep 2012 15:40:39 -0700 (PDT) Received: from anchor.twiddle.home.com ([173.160.232.49]) by mx.google.com with ESMTPS id sj5sm4480267pbc.30.2012.09.27.15.40.38 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 27 Sep 2012 15:40:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 Sep 2012 15:40:01 -0700 Message-Id: <1348785610-23418-21-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1348785610-23418-1-git-send-email-rth@twiddle.net> References: <1348785610-23418-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.220.45 Cc: Alexander Graf Subject: [Qemu-devel] [PATCH 020/147] target-s390: Convert 32-bit MULTIPLY, MULTIPLY LOGICAL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-s390x/insn-data.def | 7 ++++ target-s390x/translate.c | 82 ++++++++++++++-------------------------------- 2 files changed, 32 insertions(+), 57 deletions(-) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 055113a..ca12e47 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -41,12 +41,19 @@ C(0xeb7e, ALGSI, SIY, GIE, m1_64, i2, new, m1_64, add, addu64) C(0xecdb, ALGHSIK, RIE_d, DO, r3, i2, r1, 0, add, addu64) +/* MULTIPLY */ + C(0x1c00, MR, RR_a, Z, r1p1_32s, r2_32s, new, r1_D32, mul, 0) + C(0x5c00, M, RX_a, Z, r1p1_32s, m2_32s, new, r1_D32, mul, 0) + C(0xe35c, MFY, RXY_a, GIE, r1p1_32s, m2_32s, new, r1_D32, mul, 0) /* MULTIPLY HALFWORD */ C(0x4c00, MH, RX_a, Z, r1_o, m2_16s, new, r1_32, mul, 0) C(0xe37c, MHY, RXY_a, GIE, r1_o, m2_16s, new, r1_32, mul, 0) /* MULTIPLY HALFWORD IMMEDIATE */ C(0xa70c, MHI, RI_a, Z, r1_o, i2, new, r1_32, mul, 0) C(0xa70d, MGHI, RI_a, Z, r1_o, i2, r1, 0, mul, 0) +/* MULTIPLY LOGICAL */ + C(0xb996, MLR, RRE, Z, r1p1_32u, r2_32u, new, r1_D32, mul, 0) + C(0xe396, ML, RXY_a, Z, r1p1_32u, m2_32u, new, r1_D32, mul, 0) /* MULTIPLY SINGLE */ C(0xb252, MSR, RRE, Z, r1_o, r2_o, new, r1_32, mul, 0) C(0x7100, MS, RX_a, Z, r1_o, m2_32s, new, r1_32, mul, 0) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index d409b93..66e6b60 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -1624,18 +1624,6 @@ static void disas_e3(CPUS390XState *env, DisasContext* s, int op, int r1, store_reg32_i64(r1, tmp2); tcg_temp_free_i64(tmp2); break; - case 0x96: /* ML R1,D2(X2,B2) [RXY] */ - tmp2 = tcg_temp_new_i64(); - tmp3 = load_reg((r1 + 1) & 15); - tcg_gen_ext32u_i64(tmp3, tmp3); - tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s)); - tcg_gen_mul_i64(tmp2, tmp2, tmp3); - store_reg32_i64((r1 + 1) & 15, tmp2); - tcg_gen_shri_i64(tmp2, tmp2, 32); - store_reg32_i64(r1, tmp2); - tcg_temp_free_i64(tmp2); - tcg_temp_free_i64(tmp3); - break; case 0x97: /* DL R1,D2(X2,B2) [RXY] */ /* reg(r1) = reg(r1, r1+1) % ld32(addr) */ /* reg(r1+1) = reg(r1, r1+1) / ld32(addr) */ @@ -3219,19 +3207,6 @@ static void disas_b9(CPUS390XState *env, DisasContext *s, int op, int r1, store_reg32(r1, tmp32_1); tcg_temp_free_i32(tmp32_1); break; - case 0x96: /* MLR R1,R2 [RRE] */ - /* reg(r1, r1+1) = reg(r1+1) * reg(r2) */ - tmp2 = load_reg(r2); - tmp3 = load_reg((r1 + 1) & 15); - tcg_gen_ext32u_i64(tmp2, tmp2); - tcg_gen_ext32u_i64(tmp3, tmp3); - tcg_gen_mul_i64(tmp2, tmp2, tmp3); - store_reg32_i64((r1 + 1) & 15, tmp2); - tcg_gen_shri_i64(tmp2, tmp2, 32); - store_reg32_i64(r1, tmp2); - tcg_temp_free_i64(tmp2); - tcg_temp_free_i64(tmp3); - break; case 0x97: /* DLR R1,R2 [RRE] */ /* reg(r1) = reg(r1, r1+1) % reg(r2) */ /* reg(r1+1) = reg(r1, r1+1) / reg(r2) */ @@ -3605,21 +3580,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s) tcg_temp_free_i32(tmp32_1); tcg_temp_free_i32(tmp32_2); break; - case 0x1c: /* MR R1,R2 [RR] */ - /* reg(r1, r1+1) = reg(r1+1) * reg(r2) */ - insn = ld_code2(env, s->pc); - decode_rr(s, insn, &r1, &r2); - tmp2 = load_reg(r2); - tmp3 = load_reg((r1 + 1) & 15); - tcg_gen_ext32s_i64(tmp2, tmp2); - tcg_gen_ext32s_i64(tmp3, tmp3); - tcg_gen_mul_i64(tmp2, tmp2, tmp3); - store_reg32_i64((r1 + 1) & 15, tmp2); - tcg_gen_shri_i64(tmp2, tmp2, 32); - store_reg32_i64(r1, tmp2); - tcg_temp_free_i64(tmp2); - tcg_temp_free_i64(tmp3); - break; case 0x1d: /* DR R1,R2 [RR] */ insn = ld_code2(env, s->pc); decode_rr(s, insn, &r1, &r2); @@ -3855,23 +3815,6 @@ static void disas_s390_insn(CPUS390XState *env, DisasContext *s) tcg_temp_free_i32(tmp32_1); tcg_temp_free_i32(tmp32_2); break; - case 0x5c: /* M R1,D2(X2,B2) [RX] */ - /* reg(r1, r1+1) = reg(r1+1) * *(s32*)addr */ - insn = ld_code4(env, s->pc); - tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); - tmp2 = tcg_temp_new_i64(); - tcg_gen_qemu_ld32s(tmp2, tmp, get_mem_index(s)); - tmp3 = load_reg((r1 + 1) & 15); - tcg_gen_ext32s_i64(tmp2, tmp2); - tcg_gen_ext32s_i64(tmp3, tmp3); - tcg_gen_mul_i64(tmp2, tmp2, tmp3); - store_reg32_i64((r1 + 1) & 15, tmp2); - tcg_gen_shri_i64(tmp2, tmp2, 32); - store_reg32_i64(r1, tmp2); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tmp2); - tcg_temp_free_i64(tmp3); - break; case 0x5d: /* D R1,D2(X2,B2) [RX] */ insn = ld_code4(env, s->pc); tmp3 = decode_rx(s, insn, &r1, &x2, &b2, &d2); @@ -4868,6 +4811,15 @@ static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o) store_reg32_i64(get_field(f, r1), o->out); } +static void wout_r1_D32(DisasContext *s, DisasFields *f, DisasOps *o) +{ + /* ??? Specification exception: r1 must be even. */ + int r1 = get_field(f, r1); + store_reg32_i64((r1 + 1) & 15, o->out); + tcg_gen_shri_i64(o->out, o->out, 32); + store_reg32_i64(r1, o->out); +} + static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o) { tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s)); @@ -4892,6 +4844,22 @@ static void in1_r1_o(DisasContext *s, DisasFields *f, DisasOps *o) o->g_in1 = true; } +static void in1_r1p1_32s(DisasContext *s, DisasFields *f, DisasOps *o) +{ + /* ??? Specification exception: r1 must be even. */ + int r1 = get_field(f, r1); + o->in1 = tcg_temp_new_i64(); + tcg_gen_ext32s_i64(o->in1, regs[(r1 + 1) & 15]); +} + +static void in1_r1p1_32u(DisasContext *s, DisasFields *f, DisasOps *o) +{ + /* ??? Specification exception: r1 must be even. */ + int r1 = get_field(f, r1); + o->in1 = tcg_temp_new_i64(); + tcg_gen_ext32u_i64(o->in1, regs[(r1 + 1) & 15]); +} + static void in1_r2(DisasContext *s, DisasFields *f, DisasOps *o) { o->in1 = load_reg(get_field(f, r2));