From patchwork Thu Sep 27 01:55:32 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 187255 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 5FD622C007C for ; Thu, 27 Sep 2012 11:56:21 +1000 (EST) Received: from localhost ([::1]:33646 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TH3Kt-0001Cp-Ie for incoming@patchwork.ozlabs.org; Wed, 26 Sep 2012 21:56:19 -0400 Received: from eggs.gnu.org ([208.118.235.92]:33725) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TH3KV-00010G-3m for qemu-devel@nongnu.org; Wed, 26 Sep 2012 21:55:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TH3KT-0005ic-D2 for qemu-devel@nongnu.org; Wed, 26 Sep 2012 21:55:55 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:50416) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TH3KT-0005ej-6o for qemu-devel@nongnu.org; Wed, 26 Sep 2012 21:55:53 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp2so2797089pbb.4 for ; Wed, 26 Sep 2012 18:55:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=z+8bIOKIieijrYSYPuWjxoKQrzmx+2vuB+oybLS57wQ=; b=dNBQpfC9vRj4axemgahn+k66k2ZegKW/JCIKcPGFjftGZQVa1MueL47IvajC2GiGLS tCHuQt1RvCUrf3/h3aIVXxbBGYLJJCdk2SxLkMQ+Z2cKmfzB/pLZdyY3/RKYIMze3ysv hYEFpbBvxDMhUgegJhIDfx61tCZ99kwhFcWbdKqfb/y+u8cjHLnvgey4l6TzmNnq5/7g etnwzlnYYOf97ys7Uhz63t//eV1mjyWsHJn29hzSYmCL3HDGJ08L0x0/egUozRH6coaU G+PAMnY9TpwxQ8nv+aB88KjGfFF1iN+JYQYjCEoGDsKmH8C0qnRHm3hfW2bKWkCT3xlU 5klw== Received: by 10.68.218.101 with SMTP id pf5mr7373715pbc.60.1348710952614; Wed, 26 Sep 2012 18:55:52 -0700 (PDT) Received: from anchor.twiddle.home.com ([173.160.232.49]) by mx.google.com with ESMTPS id o1sm2830071pax.21.2012.09.26.18.55.51 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 26 Sep 2012 18:55:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 26 Sep 2012 18:55:32 -0700 Message-Id: <1348710942-3040-3-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1348710942-3040-1-git-send-email-rth@twiddle.net> References: <1348710942-3040-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Blue Swirl Subject: [Qemu-devel] [PATCH 02/12] tcg-sparc: Implement movcond. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c | 43 ++++++++++++++++++++++++++++++++++++------- tcg/sparc/tcg-target.h | 4 ++-- 2 files changed, 38 insertions(+), 9 deletions(-) diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index 726fb9b..c10e3b1 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -539,6 +539,22 @@ static void tcg_out_brcond_i32(TCGContext *s, TCGCond cond, tcg_out_nop(s); } +static void tcg_out_movcc(TCGContext *s, TCGCond cond, int cc, TCGArg ret, + TCGArg v1, int v1const) +{ + tcg_out32(s, ARITH_MOVCC | cc | INSN_RD(ret) + | INSN_RS1(tcg_cond_to_bcond[cond]) + | (v1const ? INSN_IMM11(v1) : INSN_RS2(v1))); +} + +static void tcg_out_movcond_i32(TCGContext *s, TCGCond cond, TCGArg ret, + TCGArg c1, TCGArg c2, int c2const, + TCGArg v1, int v1const) +{ + tcg_out_cmp(s, c1, c2, c2const); + tcg_out_movcc(s, cond, MOVCC_ICC, ret, v1, v1const); +} + #if TCG_TARGET_REG_BITS == 64 static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, TCGArg arg1, TCGArg arg2, int const_arg2, @@ -548,6 +564,14 @@ static void tcg_out_brcond_i64(TCGContext *s, TCGCond cond, tcg_out_branch_i64(s, tcg_cond_to_bcond[cond], label_index); tcg_out_nop(s); } + +static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGArg ret, + TCGArg c1, TCGArg c2, int c2const, + TCGArg v1, int v1const) +{ + tcg_out_cmp(s, c1, c2, c2const); + tcg_out_movcc(s, cond, MOVCC_XCC, ret, v1, v1const); +} #else static void tcg_out_brcond2_i32(TCGContext *s, TCGCond cond, TCGArg al, TCGArg ah, @@ -621,9 +645,7 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGArg ret, default: tcg_out_cmp(s, c1, c2, c2const); tcg_out_movi_imm13(s, ret, 0); - tcg_out32(s, ARITH_MOVCC | INSN_RD(ret) - | INSN_RS1(tcg_cond_to_bcond[cond]) - | MOVCC_ICC | INSN_IMM11(1)); + tcg_out_movcc(s, cond, MOVCC_ICC, ret, 1, 1); return; } @@ -641,9 +663,7 @@ static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGArg ret, { tcg_out_cmp(s, c1, c2, c2const); tcg_out_movi_imm13(s, ret, 0); - tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret) - | INSN_RS1(tcg_cond_to_bcond[cond]) - | MOVCC_XCC | INSN_IMM11(1)); + tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1); } #else static void tcg_out_setcond2_i32(TCGContext *s, TCGCond cond, TCGArg ret, @@ -1203,6 +1223,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_setcond_i32(s, args[3], args[0], args[1], args[2], const_args[2]); break; + case INDEX_op_movcond_i32: + tcg_out_movcond_i32(s, args[5], args[0], args[1], + args[2], const_args[2], args[3], const_args[3]); + break; #if TCG_TARGET_REG_BITS == 32 case INDEX_op_brcond2_i32: @@ -1338,7 +1362,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_setcond_i64(s, args[3], args[0], args[1], args[2], const_args[2]); break; - + case INDEX_op_movcond_i64: + tcg_out_movcond_i64(s, args[5], args[0], args[1], + args[2], const_args[2], args[3], const_args[3]); + break; #endif gen_arith: tcg_out_arithc(s, args[0], args[1], args[2], const_args[2], c); @@ -1394,6 +1421,7 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_brcond_i32, { "r", "rJ" } }, { INDEX_op_setcond_i32, { "r", "r", "rJ" } }, + { INDEX_op_movcond_i32, { "r", "r", "rJ", "rI", "0" } }, #if TCG_TARGET_REG_BITS == 32 { INDEX_op_brcond2_i32, { "r", "r", "rJ", "rJ" } }, @@ -1443,6 +1471,7 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_brcond_i64, { "r", "rJ" } }, { INDEX_op_setcond_i64, { "r", "r", "rJ" } }, + { INDEX_op_movcond_i64, { "r", "r", "rJ", "rI", "0" } }, #endif #if TCG_TARGET_REG_BITS == 64 diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 6314ffb..c718a52 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -99,7 +99,7 @@ typedef enum { #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 #define TCG_TARGET_HAS_deposit_i32 0 -#define TCG_TARGET_HAS_movcond_i32 0 +#define TCG_TARGET_HAS_movcond_i32 1 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_div_i64 1 @@ -121,7 +121,7 @@ typedef enum { #define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nor_i64 0 #define TCG_TARGET_HAS_deposit_i64 0 -#define TCG_TARGET_HAS_movcond_i64 0 +#define TCG_TARGET_HAS_movcond_i64 1 #endif #define TCG_TARGET_HAS_GUEST_BASE