From patchwork Sat Sep 22 02:05:01 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 186039 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D704A2C0092 for ; Sat, 22 Sep 2012 12:35:51 +1000 (EST) Received: from localhost ([::1]:42231 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TFF6X-0006g7-5v for incoming@patchwork.ozlabs.org; Fri, 21 Sep 2012 22:06:01 -0400 Received: from eggs.gnu.org ([208.118.235.92]:57528) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TFF5v-0005K8-Di for qemu-devel@nongnu.org; Fri, 21 Sep 2012 22:05:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TFF5u-0000lQ-5o for qemu-devel@nongnu.org; Fri, 21 Sep 2012 22:05:23 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:64906) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TFF5t-0000d7-Tn for qemu-devel@nongnu.org; Fri, 21 Sep 2012 22:05:22 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp12so8850169pbb.4 for ; Fri, 21 Sep 2012 19:05:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=hnkBdJwUyzVpjdH4HFDQZ74xxtA4y7uMrIHADvwb7jM=; b=Q4n8JBDErclEsQmihJoJIT6kuDT0ViOdRON5v7zDSQNkYftoSEARHauB/8FqSPbDLy 8WPhHEW6Y73l4E5NQ+sHdX6q4YCbR4nMG9VQvd44KchewTZSjl1dHSTHmHgfVgTjjBIQ l78J2E8exqQ6y8z+lcrzF+LfTFOJVOmJWE7H+j2ZpTkuTkJV4DTsuI2c3M4F2z4e7UhR wFeNQJUnayMFhs4LgFYmvV6rGbsFHmJbKOnyvynLOTsPdxYSO4nKLN3OvKgVQ0mXhZoc tTNbksZG+2N+oRlfJzDxUtk/8L+ikYXoF7Ok6pKYExZXQKseMztMMwchNbccfWcFFAVR 4OEQ== Received: by 10.68.225.68 with SMTP id ri4mr15289432pbc.115.1348279521455; Fri, 21 Sep 2012 19:05:21 -0700 (PDT) Received: from anchor.twiddle.home.com ([173.160.232.49]) by mx.google.com with ESMTPS id s4sm4956298paw.35.2012.09.21.19.05.20 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 21 Sep 2012 19:05:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 21 Sep 2012 19:05:01 -0700 Message-Id: <1348279507-3617-9-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1348279507-3617-1-git-send-email-rth@twiddle.net> References: <1348279507-3617-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Blue Swirl Subject: [Qemu-devel] [PATCH 08/14] tcg-sparc: Change AREG0 in generated code to %i0. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We can now move the TCG variable from %g[56] to a call-preserved windowed register. Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c | 3 ++- tcg/sparc/tcg-target.h | 8 +------- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index 5acfeba..9ab5746 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -696,7 +696,8 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I1) | INSN_RS2(TCG_REG_G0)); - tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_I0); + /* delay slot */ + tcg_out_nop(s); } #if defined(CONFIG_SOFTMMU) diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 99e9f57..ee154d0 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -130,13 +130,7 @@ typedef enum { #define TCG_TARGET_HAS_GUEST_BASE -#ifdef CONFIG_SOLARIS -#define TCG_AREG0 TCG_REG_G2 -#elif HOST_LONG_BITS == 64 -#define TCG_AREG0 TCG_REG_G5 -#else -#define TCG_AREG0 TCG_REG_G6 -#endif +#define TCG_AREG0 TCG_REG_I0 static inline void flush_icache_range(tcg_target_ulong start, tcg_target_ulong stop)