From patchwork Sat Sep 22 02:05:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 186065 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0A4332C0079 for ; Sat, 22 Sep 2012 12:48:15 +1000 (EST) Received: from localhost ([::1]:42230 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TFF6U-0006g5-C8 for incoming@patchwork.ozlabs.org; Fri, 21 Sep 2012 22:05:58 -0400 Received: from eggs.gnu.org ([208.118.235.92]:57527) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TFF5v-0005K3-Dh for qemu-devel@nongnu.org; Fri, 21 Sep 2012 22:05:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TFF5t-0000kO-Cb for qemu-devel@nongnu.org; Fri, 21 Sep 2012 22:05:23 -0400 Received: from mail-pa0-f45.google.com ([209.85.220.45]:64832) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TFF5t-0000kG-6l for qemu-devel@nongnu.org; Fri, 21 Sep 2012 22:05:21 -0400 Received: by padfb10 with SMTP id fb10so615289pad.4 for ; Fri, 21 Sep 2012 19:05:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=3RaRjz+kxybqPYmA5eaPvinLRpH4x6JPtw2ZLLSOqoo=; b=xpNFrruFiB2nsCaBcR/RpyXebO7VCPA8e7p9PmGpaa3ddTbDR+7LBEDiFts+/Yd9JU uMh1VIMKYE9+rF5FNvs3GMgD0HXUTIZQU8IodTAGW0BTuH8bQvJEg3OzevHXfjYjMkfn gnyEQwZtecTaOLpn+k1RdozTbVRXpudxKhWtkM7MyqxlXx8D2t7IRWsGTaWBWOleKMiv 5LYS9DAnlrkoZCg6UrEEEQB8827lCs1MZ82NJqWzc0TjrAKncdG7j067dzYqNiAf4HVY ZAmVQkc4UA0EsBobW8ZPjqyqPLMlpDjcef1BzN+8M50TVW8vo9mtx0iaG2FxQH0N5vH2 E2sw== Received: by 10.68.224.138 with SMTP id rc10mr19966856pbc.34.1348279520579; Fri, 21 Sep 2012 19:05:20 -0700 (PDT) Received: from anchor.twiddle.home.com ([173.160.232.49]) by mx.google.com with ESMTPS id s4sm4956298paw.35.2012.09.21.19.05.19 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 21 Sep 2012 19:05:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 21 Sep 2012 19:05:00 -0700 Message-Id: <1348279507-3617-8-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1348279507-3617-1-git-send-email-rth@twiddle.net> References: <1348279507-3617-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.220.45 Cc: Blue Swirl Subject: [Qemu-devel] [PATCH 07/14] tcg-sparc: Support GUEST_BASE. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- configure | 2 ++ tcg/sparc/tcg-target.c | 26 +++++++++++++++++++++++--- tcg/sparc/tcg-target.h | 2 ++ 3 files changed, 27 insertions(+), 3 deletions(-) diff --git a/configure b/configure index df888f2..0dc4170 100755 --- a/configure +++ b/configure @@ -870,6 +870,7 @@ case "$cpu" in if test "$solaris" = "no" ; then QEMU_CFLAGS="-ffixed-g1 -ffixed-g6 $QEMU_CFLAGS" fi + host_guest_base="yes" ;; sparc64) LDFLAGS="-m64 $LDFLAGS" @@ -878,6 +879,7 @@ case "$cpu" in if test "$solaris" != "no" ; then QEMU_CFLAGS="-ffixed-g1 $QEMU_CFLAGS" fi + host_guest_base="yes" ;; s390) QEMU_CFLAGS="-m31 -march=z990 $QEMU_CFLAGS" diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index d89c19b..5acfeba 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -59,6 +59,12 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { }; #endif +#ifdef CONFIG_USE_GUEST_BASE +# define TCG_GUEST_BASE_REG TCG_REG_I3 +#else +# define TCG_GUEST_BASE_REG TCG_REG_G0 +#endif + static const int tcg_target_reg_alloc_order[] = { TCG_REG_L0, TCG_REG_L1, @@ -680,6 +686,14 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) | INSN_IMM13(-(TCG_TARGET_STACK_MINFRAME + CPU_TEMP_BUF_NLONGS * (int)sizeof(long)))); + +#ifdef CONFIG_USE_GUEST_BASE + if (GUEST_BASE != 0) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, GUEST_BASE); + tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); + } +#endif + tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I1) | INSN_RS2(TCG_REG_G0)); tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_I0); @@ -925,14 +939,18 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int sizeop) if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) { int reg64 = (datalo < 16 ? datalo : TCG_REG_O0); - tcg_out_ldst_rr(s, reg64, addr_reg, TCG_REG_G0, qemu_ld_opc[sizeop]); + tcg_out_ldst_rr(s, reg64, addr_reg, + (GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0), + qemu_ld_opc[sizeop]); tcg_out_arithi(s, datahi, reg64, 32, SHIFT_SRLX); if (reg64 != datalo) { tcg_out_mov(s, TCG_TYPE_I32, datalo, reg64); } } else { - tcg_out_ldst_rr(s, datalo, addr_reg, TCG_REG_G0, qemu_ld_opc[sizeop]); + tcg_out_ldst_rr(s, datalo, addr_reg, + (GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0), + qemu_ld_opc[sizeop]); } #endif /* CONFIG_SOFTMMU */ } @@ -1026,7 +1044,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int sizeop) tcg_out_arith(s, TCG_REG_G1, TCG_REG_G1, TCG_REG_O2, ARITH_OR); datalo = TCG_REG_G1; } - tcg_out_ldst_rr(s, datalo, addr_reg, TCG_REG_G0, qemu_st_opc[sizeop]); + tcg_out_ldst_rr(s, datalo, addr_reg, + (GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0), + qemu_st_opc[sizeop]); #endif /* CONFIG_SOFTMMU */ } diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index adca1d2..99e9f57 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -128,6 +128,8 @@ typedef enum { #define TCG_TARGET_HAS_movcond_i64 0 #endif +#define TCG_TARGET_HAS_GUEST_BASE + #ifdef CONFIG_SOLARIS #define TCG_AREG0 TCG_REG_G2 #elif HOST_LONG_BITS == 64