From patchwork Wed Sep 19 20:00:23 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 185212 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E52882C007D for ; Thu, 20 Sep 2012 06:01:31 +1000 (EST) Received: from localhost ([::1]:55263 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TEQSg-0005wh-2H for incoming@patchwork.ozlabs.org; Wed, 19 Sep 2012 16:01:30 -0400 Received: from eggs.gnu.org ([208.118.235.92]:42121) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TEQRl-0003bv-Qz for qemu-devel@nongnu.org; Wed, 19 Sep 2012 16:00:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TEQRg-0002Bw-PA for qemu-devel@nongnu.org; Wed, 19 Sep 2012 16:00:33 -0400 Received: from hall.aurel32.net ([88.191.126.93]:52044) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TEQRg-00029S-Id for qemu-devel@nongnu.org; Wed, 19 Sep 2012 16:00:28 -0400 Received: from [2001:470:d4ed:1:2db:dfff:fe14:52d] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TEQRf-00052V-5m; Wed, 19 Sep 2012 22:00:27 +0200 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TEQRd-0004pH-Fh; Wed, 19 Sep 2012 22:00:25 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Wed, 19 Sep 2012 22:00:23 +0200 Message-Id: <1348084823-18277-10-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1348084823-18277-1-git-send-email-aurelien@aurel32.net> References: <1348084823-18277-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 88.191.126.93 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH 9/9] tcg: remove #ifdef #endif around TCGOpcode tests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Commit 25c4d9cc changed all TCGOpcode enums to be available, so we don't need to #ifdef #endif the one that are available only on some targets. This makes the code easier to read. Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson --- tcg/tcg.c | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index b8a1bec..57fca70 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -937,11 +937,7 @@ void tcg_dump_ops(TCGContext *s) args[nb_oargs + i])); } } - } else if (c == INDEX_op_movi_i32 -#if TCG_TARGET_REG_BITS == 64 - || c == INDEX_op_movi_i64 -#endif - ) { + } else if (c == INDEX_op_movi_i32 || c == INDEX_op_movi_i64) { tcg_target_ulong val; TCGHelperInfo *th; @@ -991,17 +987,11 @@ void tcg_dump_ops(TCGContext *s) } switch (c) { case INDEX_op_brcond_i32: -#if TCG_TARGET_REG_BITS == 32 case INDEX_op_brcond2_i32: -#elif TCG_TARGET_REG_BITS == 64 case INDEX_op_brcond_i64: -#endif case INDEX_op_setcond_i32: -#if TCG_TARGET_REG_BITS == 32 case INDEX_op_setcond2_i32: -#elif TCG_TARGET_REG_BITS == 64 case INDEX_op_setcond_i64: -#endif if (args[k] < ARRAY_SIZE(cond_name) && cond_name[args[k]]) { qemu_log(",%s", cond_name[args[k++]]); } else { @@ -2103,16 +2093,12 @@ static inline int tcg_gen_code_common(TCGContext *s, uint8_t *gen_code_buf, #endif switch(opc) { case INDEX_op_mov_i32: -#if TCG_TARGET_REG_BITS == 64 case INDEX_op_mov_i64: -#endif dead_args = s->op_dead_args[op_index]; tcg_reg_alloc_mov(s, def, args, dead_args); break; case INDEX_op_movi_i32: -#if TCG_TARGET_REG_BITS == 64 case INDEX_op_movi_i64: -#endif tcg_reg_alloc_movi(s, args); break; case INDEX_op_debug_insn_start: