From patchwork Mon Sep 17 21:35:11 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 184569 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 673162C007F for ; Tue, 18 Sep 2012 08:14:27 +1000 (EST) Received: from localhost ([::1]:55820 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDizC-0002YQ-Fb for incoming@patchwork.ozlabs.org; Mon, 17 Sep 2012 17:36:10 -0400 Received: from eggs.gnu.org ([208.118.235.92]:50031) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDiyZ-0001Ib-VU for qemu-devel@nongnu.org; Mon, 17 Sep 2012 17:35:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TDiyX-0006ys-DN for qemu-devel@nongnu.org; Mon, 17 Sep 2012 17:35:31 -0400 Received: from mail-qa0-f52.google.com ([209.85.216.52]:43089) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDiyX-0006w7-9G for qemu-devel@nongnu.org; Mon, 17 Sep 2012 17:35:29 -0400 Received: by mail-qa0-f52.google.com with SMTP id g14so1916212qab.4 for ; Mon, 17 Sep 2012 14:35:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=L+KzLhFXzkPc6o2RFaDwAEC9IFMfLRi+erQ2J6G2T8Q=; b=BaKXNgE/IDfD3rf3cs+a2ti1LZ219FTh6olU7Gnl0MRAc3AgA9luRhV+1XIlU2JZCU vLCXE9bMDhRkeBThx//vsRZ79UNX/5nUE2+2J4v1yR415tGcz6iCgd+NAAlzFmPuYDIa B25PF91O/I0SOQBwTbkY6GE8EyPt9A/XxXvAVlKdKumLK4I+BItr7rrJ3gY8Kf0x01fS F9ejHGj6B6tIXoG2v/pQ3q9M/TAJjNIe7gL6fhIKMCslsiaOgvmK6h6BkzzAlifUG1/q cngqFiCiCsy81//sRV0xr4h+akUDGYyK8fURsMnV/X97ot+Qf2xp2SGmp4PyZyRCFCTe rOCw== Received: by 10.229.134.202 with SMTP id k10mr8266147qct.71.1347917728901; Mon, 17 Sep 2012 14:35:28 -0700 (PDT) Received: from anchor.twiddle.home.com ([173.160.232.49]) by mx.google.com with ESMTPS id h8sm16725178qap.16.2012.09.17.14.35.27 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 17 Sep 2012 14:35:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Sep 2012 14:35:11 -0700 Message-Id: <1347917713-23343-6-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1347917713-23343-1-git-send-email-rth@twiddle.net> References: <1347917713-23343-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.216.52 Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 5/7] target-mips: Use TCG registers for the FPU. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org With normal FP, this doesn't have much affect on the generated code, because most of the FP operations are not CONST/PURE, and so we spill registers in about the same frequency as the explicit load/stores. But with Loongson multimedia instructions, which are all integral and whose helpers are in fact CONST+PURE, this greatly improves the code. Rather than over-use the deposit operation, we create TCG registers for both the 64-bit FPU register as a whole and the two 32-bit halves. We only ever reference the whole register or the two half registers in any one TB, so there's no problem with aliasing. Signed-off-by: Richard Henderson --- target-mips/translate.c | 141 +++++++++++++++++++++++++++++++++--------------- 1 file changed, 97 insertions(+), 44 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index b4301e9..df92cec 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -479,6 +479,12 @@ static TCGv cpu_dspctrl, btarget, bcond; static TCGv_i32 hflags; static TCGv_i32 fpu_fcr0, fpu_fcr31; +/* FPU registers. These alias, but we'll only use one or the other + in any one TB based on MIPS_HFLAG_F64. */ +static TCGv_i32 fpu_f32[32]; +static TCGv_i32 fpu_fh32[32]; +static TCGv_i64 fpu_f64[32]; + static uint32_t gen_opc_hflags[OPC_BUF_SIZE]; #include "gen-icount.h" @@ -545,26 +551,45 @@ enum { BS_EXCP = 3, /* We reached an exception condition */ }; -static const char *regnames[] = - { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", - "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", - "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", }; +static const char * const regnames[] = { + "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", + "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", +}; + +static const char * const regnames_HI[] = { + "HI0", "HI1", "HI2", "HI3", +}; -static const char *regnames_HI[] = - { "HI0", "HI1", "HI2", "HI3", }; +static const char * const regnames_LO[] = { + "LO0", "LO1", "LO2", "LO3", +}; -static const char *regnames_LO[] = - { "LO0", "LO1", "LO2", "LO3", }; +static const char * const regnames_ACX[] = { + "ACX0", "ACX1", "ACX2", "ACX3", +}; -static const char *regnames_ACX[] = - { "ACX0", "ACX1", "ACX2", "ACX3", }; +static const char * const fregnames[] = { + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", +}; -static const char *fregnames[] = - { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", - "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", - "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", - "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", }; +static const char * const flregnames[] = { + "fl0", "fl1", "fl2", "fl3", "fl4", "fl5", "fl6", "fl7", + "fl8", "fl9", "fl10", "fl11", "fl12", "fl13", "fl14", "fl15", + "fl16", "fl17", "fl18", "fl19", "fl20", "fl21", "fl22", "fl23", + "fl24", "fl25", "fl26", "fl27", "fl28", "fl29", "fl30", "fl31", +}; + +static const char * const fhregnames[] = { + "fh0", "fh1", "fh2", "fh3", "fh4", "fh5", "fh6", "fh7", + "fh8", "fh9", "fh10", "fh11", "fh12", "fh13", "fh14", "fh15", + "fh16", "fh17", "fh18", "fh19", "fh20", "fh21", "fh22", "fh23", + "fh24", "fh25", "fh26", "fh27", "fh28", "fh29", "fh30", "fh31", +}; #ifdef MIPS_DEBUG_DISAS #define MIPS_DEBUG(fmt, ...) \ @@ -662,55 +687,70 @@ static inline void gen_store_srsgpr (int from, int to) } /* Floating point register moves. */ -static inline void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) +static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) { - tcg_gen_ld_i32(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX])); + if (ctx->hflags & MIPS_HFLAG_F64) { + tcg_gen_trunc_i64_i32(t, fpu_f64[reg]); + } else { + tcg_gen_mov_i32(t, fpu_f32[reg]); + } } -static inline void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) +static void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) { - tcg_gen_st_i32(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX])); + if (ctx->hflags & MIPS_HFLAG_F64) { + TCGv_i64 t64 = tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(t64, t); + tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 0, 32); + tcg_temp_free_i64(t64); + } else { + tcg_gen_mov_i32(fpu_f32[reg], t); + } } -static inline void gen_load_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg) +static void gen_load_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg) { - tcg_gen_ld_i32(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX])); + if (ctx->hflags & MIPS_HFLAG_F64) { + TCGv_i64 t64 = tcg_temp_new_i64(); + tcg_gen_shri_i64(t64, fpu_f64[reg], 32); + tcg_gen_trunc_i64_i32(t, t64); + tcg_temp_free_i64(t64); + } else { + tcg_gen_mov_i32(t, fpu_fh32[reg]); + } } -static inline void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg) +static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg) { - tcg_gen_st_i32(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX])); + if (ctx->hflags & MIPS_HFLAG_F64) { + TCGv_i64 t64 = tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(t64, t); + tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 32, 32); + tcg_temp_free_i64(t64); + } else { + tcg_gen_mov_i32(fpu_fh32[reg], t); + } } -static inline void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) +static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { if (ctx->hflags & MIPS_HFLAG_F64) { - tcg_gen_ld_i64(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].d)); + tcg_gen_mov_i64(t, fpu_f64[reg]); } else { - TCGv_i32 t0 = tcg_temp_new_i32(); - TCGv_i32 t1 = tcg_temp_new_i32(); - gen_load_fpr32(ctx, t0, reg & ~1); - gen_load_fpr32(ctx, t1, reg | 1); - tcg_gen_concat_i32_i64(t, t0, t1); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); + tcg_gen_concat_i32_i64(t, fpu_f32[reg & ~1], fpu_f32[reg | 1]); } } -static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) +static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { if (ctx->hflags & MIPS_HFLAG_F64) { - tcg_gen_st_i64(t, cpu_env, offsetof(CPUMIPSState, active_fpu.fpr[reg].d)); + tcg_gen_mov_i64(fpu_f64[reg], t); } else { - TCGv_i64 t0 = tcg_temp_new_i64(); - TCGv_i32 t1 = tcg_temp_new_i32(); - tcg_gen_trunc_i64_i32(t1, t); - gen_store_fpr32(ctx, t1, reg & ~1); - tcg_gen_shri_i64(t0, t, 32); - tcg_gen_trunc_i64_i32(t1, t0); - gen_store_fpr32(ctx, t1, reg | 1); - tcg_temp_free_i32(t1); - tcg_temp_free_i64(t0); + TCGv_i64 t64 = tcg_temp_new_i64(); + tcg_gen_shri_i64(t64, t, 32); + tcg_gen_trunc_i64_i32(fpu_f32[reg | 1], t64); + tcg_temp_free_i64(t64); + tcg_gen_trunc_i64_i32(fpu_f32[reg & ~1], t); } } @@ -12694,6 +12734,19 @@ static void mips_tcg_init(void) offsetof(CPUMIPSState, active_fpu.fcr31), "fcr31"); + for (i = 0; i < 32; i++) { + int off = offsetof(CPUMIPSState, active_fpu.fpr[i].w[FP_ENDIAN_IDX]); + fpu_f32[i] = tcg_global_mem_new_i32(TCG_AREG0, off, flregnames[i]); + } + for (i = 0; i < 32; i++) { + int off = offsetof(CPUMIPSState, active_fpu.fpr[i].w[!FP_ENDIAN_IDX]); + fpu_fh32[i] = tcg_global_mem_new_i32(TCG_AREG0, off, fhregnames[i]); + } + for (i = 0; i < 32; i++) { + int off = offsetof(CPUMIPSState, active_fpu.fpr[i].w[FP_ENDIAN_IDX]); + fpu_f64[i] = tcg_global_mem_new_i64(TCG_AREG0, off, fregnames[i]); + } + /* register helpers */ #define GEN_HELPER 2 #include "helper.h"