From patchwork Mon Sep 17 15:28:48 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 184468 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id C64612C0084 for ; Tue, 18 Sep 2012 01:36:21 +1000 (EST) Received: from localhost ([::1]:33177 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDdGu-0006Kv-Ai for incoming@patchwork.ozlabs.org; Mon, 17 Sep 2012 11:30:04 -0400 Received: from eggs.gnu.org ([208.118.235.92]:40296) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDdG7-0004Zf-2H for qemu-devel@nongnu.org; Mon, 17 Sep 2012 11:29:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TDdG5-0005mL-Md for qemu-devel@nongnu.org; Mon, 17 Sep 2012 11:29:14 -0400 Received: from mail-qa0-f52.google.com ([209.85.216.52]:51587) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDdG5-0005gZ-J8 for qemu-devel@nongnu.org; Mon, 17 Sep 2012 11:29:13 -0400 Received: by mail-qa0-f52.google.com with SMTP id g14so1598216qab.4 for ; Mon, 17 Sep 2012 08:29:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=GXAUgQsR+bXds2RqUKHA6+IkhZJR/RrGbJPlSGzO9FI=; b=D1tb4Lt6CGKJplCM+pMe0ggc7fwbV6YbOLHi6Mas7aesz1NCm5p+y3PIc8FX8AmuKC UimxZeA7nk6bvwju65y4UhVhr1rqzgMD+fmSMJyd7zgnYCFcejsgKUfRSnP/30vnK0eP qDH9tHiW54fu3Wrris5QvWXWx6ZFrhHOa3KdBmCUuulKzCQOMpYeX8oSuhY1VNl6otBd S4/YO/SKu/s9A1WfGpqGFrPFZDBh2j66i1dPmo2THbAoeLJuI2EH2mG5LGrd8nVY0cFw aXZQhgbUD9w0TVdmXtejlKpreBrqCzaP1Yo5m90tFs1Vxn0c7BOc1V3VGtAUqY2a3OoT H8ow== Received: by 10.229.135.75 with SMTP id m11mr7614065qct.66.1347895753408; Mon, 17 Sep 2012 08:29:13 -0700 (PDT) Received: from anchor.twiddle.home.com ([173.160.232.49]) by mx.google.com with ESMTPS id d11sm13593751qaj.18.2012.09.17.08.29.12 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 17 Sep 2012 08:29:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Sep 2012 08:28:48 -0700 Message-Id: <1347895732-22212-10-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1347895732-22212-1-git-send-email-rth@twiddle.net> References: <1347895732-22212-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.216.52 Cc: blauwirbel@gmail.com Subject: [Qemu-devel] [PATCH 09/13] tcg-sparc: Mask shift immediates to avoid illegal insns. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The xtensa-test image generates a sra_i32 with count 0x40. Whether this is accident of tcg constant propagation or originating directly from the instruction stream is immaterial. Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index e625aa3..be5c170 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -1154,13 +1154,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, goto gen_arith; case INDEX_op_shl_i32: c = SHIFT_SLL; - goto gen_arith; + do_shift32: + /* Limit immediate shift count lest we create an illegal insn. */ + tcg_out_arithc(s, args[0], args[1], args[2] & 31, const_args[2], c); + break; case INDEX_op_shr_i32: c = SHIFT_SRL; - goto gen_arith; + goto do_shift32; case INDEX_op_sar_i32: c = SHIFT_SRA; - goto gen_arith; + goto do_shift32; case INDEX_op_mul_i32: c = ARITH_UMUL; goto gen_arith; @@ -1281,13 +1284,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_shl_i64: c = SHIFT_SLLX; - goto gen_arith; + do_shift64: + /* Limit immediate shift count lest we create an illegal insn. */ + tcg_out_arithc(s, args[0], args[1], args[2] & 63, const_args[2], c); + break; case INDEX_op_shr_i64: c = SHIFT_SRLX; - goto gen_arith; + goto do_shift64; case INDEX_op_sar_i64: c = SHIFT_SRAX; - goto gen_arith; + goto do_shift64; case INDEX_op_mul_i64: c = ARITH_MULX; goto gen_arith;