From patchwork Sun Sep 16 23:11:55 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 184180 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A78A22C0080 for ; Mon, 17 Sep 2012 09:12:20 +1000 (EST) Received: from localhost ([::1]:37406 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDO0g-0000zv-KG for incoming@patchwork.ozlabs.org; Sun, 16 Sep 2012 19:12:18 -0400 Received: from eggs.gnu.org ([208.118.235.92]:52645) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDO0T-0000wq-QD for qemu-devel@nongnu.org; Sun, 16 Sep 2012 19:12:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TDO0R-0008AO-N7 for qemu-devel@nongnu.org; Sun, 16 Sep 2012 19:12:05 -0400 Received: from hall.aurel32.net ([88.191.126.93]:47763) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDO0R-00089m-GR for qemu-devel@nongnu.org; Sun, 16 Sep 2012 19:12:03 -0400 Received: from [2001:470:d4ed:0:ea11:32ff:fea1:831a] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TDO0Q-0006U6-F3; Mon, 17 Sep 2012 01:12:02 +0200 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TDO0P-0003nI-TU; Mon, 17 Sep 2012 01:12:01 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Mon, 17 Sep 2012 01:11:55 +0200 Message-Id: <1347837120-14422-7-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1347837120-14422-1-git-send-email-aurelien@aurel32.net> References: <1347837120-14422-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 88.191.126.93 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH 06/11] target-sh4: optimize swap.w X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org It's possible swap the two 16-bit words of a 32-bit register using a rotation. If the TCG target doesn't implement rotation, the replacement code is similar to the previously implemented code. Signed-off-by: Aurelien Jarno --- target-sh4/translate.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 92c5a1f..9ecbe47 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -732,17 +732,7 @@ static void _decode_opc(DisasContext * ctx) } return; case 0x6009: /* swap.w Rm,Rn */ - { - TCGv high, low; - high = tcg_temp_new(); - tcg_gen_shli_i32(high, REG(B7_4), 16); - low = tcg_temp_new(); - tcg_gen_shri_i32(low, REG(B7_4), 16); - tcg_gen_ext16u_i32(low, low); - tcg_gen_or_i32(REG(B11_8), high, low); - tcg_temp_free(low); - tcg_temp_free(high); - } + tcg_gen_rotli_i32(REG(B11_8), REG(B7_4), 16); return; case 0x200d: /* xtrct Rm,Rn */ {