From patchwork Sun Sep 16 23:11:53 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 184267 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E3C9B2C00D9 for ; Mon, 17 Sep 2012 09:58:35 +1000 (EST) Received: from localhost ([::1]:41150 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDO1J-00030W-Kj for incoming@patchwork.ozlabs.org; Sun, 16 Sep 2012 19:12:57 -0400 Received: from eggs.gnu.org ([208.118.235.92]:52681) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDO0U-0000wz-IF for qemu-devel@nongnu.org; Sun, 16 Sep 2012 19:12:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TDO0R-0008Ad-Oo for qemu-devel@nongnu.org; Sun, 16 Sep 2012 19:12:06 -0400 Received: from hall.aurel32.net ([88.191.126.93]:47762) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TDO0R-00089h-GA for qemu-devel@nongnu.org; Sun, 16 Sep 2012 19:12:03 -0400 Received: from [2001:470:d4ed:0:ea11:32ff:fea1:831a] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TDO0Q-0006U3-98; Mon, 17 Sep 2012 01:12:02 +0200 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TDO0P-0003n8-RQ; Mon, 17 Sep 2012 01:12:01 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Mon, 17 Sep 2012 01:11:53 +0200 Message-Id: <1347837120-14422-5-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1347837120-14422-1-git-send-email-aurelien@aurel32.net> References: <1347837120-14422-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 88.191.126.93 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH 04/11] target-sh4: implement addv and subv using TCG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org addv and subv helpers implementation is directly copied from the SH4 manual and looks quite complex. It is however possible to explain it without branches, and is therefore possible to implement it with TCG. Signed-off-by: Aurelien Jarno --- target-sh4/helper.h | 2 -- target-sh4/op_helper.c | 58 ------------------------------------------------ target-sh4/translate.c | 36 ++++++++++++++++++++++++++++-- 3 files changed, 34 insertions(+), 62 deletions(-) diff --git a/target-sh4/helper.h b/target-sh4/helper.h index 92d6dd7..a00b7dd 100644 --- a/target-sh4/helper.h +++ b/target-sh4/helper.h @@ -13,8 +13,6 @@ DEF_HELPER_3(movcal, void, env, i32, i32) DEF_HELPER_1(discard_movcal_backup, void, env) DEF_HELPER_2(ocbi, void, env, i32) -DEF_HELPER_3(addv, i32, env, i32, i32) -DEF_HELPER_3(subv, i32, env, i32, i32) DEF_HELPER_3(div1, i32, env, i32, i32) DEF_HELPER_3(macl, void, env, i32, i32) DEF_HELPER_3(macw, void, env, i32, i32) diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c index 3ad10ba..4f1f754 100644 --- a/target-sh4/op_helper.c +++ b/target-sh4/op_helper.c @@ -177,35 +177,6 @@ void helper_ocbi(CPUSH4State *env, uint32_t address) } } -uint32_t helper_addv(CPUSH4State *env, uint32_t arg0, uint32_t arg1) -{ - uint32_t dest, src, ans; - - if ((int32_t) arg1 >= 0) - dest = 0; - else - dest = 1; - if ((int32_t) arg0 >= 0) - src = 0; - else - src = 1; - src += dest; - arg1 += arg0; - if ((int32_t) arg1 >= 0) - ans = 0; - else - ans = 1; - ans += dest; - if (src == 0 || src == 2) { - if (ans == 1) - env->sr |= SR_T; - else - env->sr &= ~SR_T; - } else - env->sr &= ~SR_T; - return arg1; -} - #define T (env->sr & SR_T) #define Q (env->sr & SR_Q ? 1 : 0) #define M (env->sr & SR_M ? 1 : 0) @@ -359,35 +330,6 @@ void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1) } } -uint32_t helper_subv(CPUSH4State *env, uint32_t arg0, uint32_t arg1) -{ - int32_t dest, src, ans; - - if ((int32_t) arg1 >= 0) - dest = 0; - else - dest = 1; - if ((int32_t) arg0 >= 0) - src = 0; - else - src = 1; - src += dest; - arg1 -= arg0; - if ((int32_t) arg1 >= 0) - ans = 0; - else - ans = 1; - ans += dest; - if (src == 1) { - if (ans == 1) - env->sr |= SR_T; - else - env->sr &= ~SR_T; - } else - env->sr &= ~SR_T; - return arg1; -} - static inline void set_t(CPUSH4State *env) { env->sr |= SR_T; diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 92f9b46..41a1f22 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -781,7 +781,23 @@ static void _decode_opc(DisasContext * ctx) } return; case 0x300f: /* addv Rm,Rn */ - gen_helper_addv(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8)); + { + TCGv t0, t1, t2; + t0 = tcg_temp_new(); + tcg_gen_add_i32(t0, REG(B7_4), REG(B11_8)); + t1 = tcg_temp_new(); + tcg_gen_xor_i32(t1, t0, REG(B11_8)); + t2 = tcg_temp_new(); + tcg_gen_xor_i32(t2, REG(B7_4), REG(B11_8)); + tcg_gen_andc_i32(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_shri_i32(t1, t1, 31); + tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); + tcg_gen_or_i32(cpu_sr, cpu_sr, t1); + tcg_temp_free(t1); + tcg_gen_mov_i32(REG(B7_4), t0); + tcg_temp_free(t0); + } return; case 0x2009: /* and Rm,Rn */ tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4)); @@ -1050,7 +1066,23 @@ static void _decode_opc(DisasContext * ctx) } return; case 0x300b: /* subv Rm,Rn */ - gen_helper_subv(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8)); + { + TCGv t0, t1, t2; + t0 = tcg_temp_new(); + tcg_gen_sub_i32(t0, REG(B11_8), REG(B7_4)); + t1 = tcg_temp_new(); + tcg_gen_xor_i32(t1, t0, REG(B7_4)); + t2 = tcg_temp_new(); + tcg_gen_xor_i32(t2, REG(B11_8), REG(B7_4)); + tcg_gen_and_i32(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_shri_i32(t1, t1, 31); + tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); + tcg_gen_or_i32(cpu_sr, cpu_sr, t1); + tcg_temp_free(t1); + tcg_gen_mov_i32(REG(B11_8), t0); + tcg_temp_free(t0); + } return; case 0x2008: /* tst Rm,Rn */ {