From patchwork Sun Sep 9 21:05:35 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 182708 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3F8AF2C00A0 for ; Mon, 10 Sep 2012 08:48:54 +1000 (EST) Received: from localhost ([::1]:33161 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAqJA-0004GW-Ed for incoming@patchwork.ozlabs.org; Sun, 09 Sep 2012 18:48:52 -0400 Received: from eggs.gnu.org ([208.118.235.92]:57049) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAojF-000075-Nw for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TAojE-0006CB-E1 for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:41 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:63059) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAojE-0005pO-90 for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:40 -0400 Received: by mail-pz0-f45.google.com with SMTP id n15so968311dad.4 for ; Sun, 09 Sep 2012 14:07:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=GUnhztRI/wb4qpOl1jksXmwdRRgHI6G7RBVZ+s503sA=; b=i+lC9M+Q/vrBV9Ca0cqV3VhkX8n+CShDPEX5yjT6OP+YUBAJ7LMqD1ioec+3doKHHi iqEnzk1OTkbme/ouxTFf0VcQy0QNXEfrYFjvnp9hVsShgZy9KAJPUBVOueT7Zp6YbQMq NKfXKPUNQItMC5p+otTeI9Q7EpdOXny3UVMON7X8po9wdu4KElwGkY/gNoERhC4gv24G ZFQZloUDA3ij5bRD87trFd+z+EMeirCOXrEuFzhOJw0UalzwfOu6msqJCwGBSFslZEbg fcC2b5/As+gJXoDmLHjdIN+Dya/v2aI/jRG051he00+NqPTmH0MTIZkOMQ5t1zIfvEB6 DTrg== Received: by 10.68.212.161 with SMTP id nl1mr2058414pbc.84.1347224860020; Sun, 09 Sep 2012 14:07:40 -0700 (PDT) Received: from anchor.twiddle.home ([173.160.232.49]) by mx.google.com with ESMTPS id tw5sm662053pbc.48.2012.09.09.14.07.39 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 09 Sep 2012 14:07:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 9 Sep 2012 14:05:35 -0700 Message-Id: <1347224784-19472-78-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1347224784-19472-1-git-send-email-rth@twiddle.net> References: <1347224784-19472-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.210.45 Cc: Alexander Graf Subject: [Qemu-devel] [PATCH 077/126] target-s390: Convert LOAD ZERO X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-s390x/fpu_helper.c | 22 ---------------------- target-s390x/helper.h | 3 --- target-s390x/insn-data.def | 4 ++++ target-s390x/translate.c | 29 ++++++++++++++--------------- 4 files changed, 18 insertions(+), 40 deletions(-) diff --git a/target-s390x/fpu_helper.c b/target-s390x/fpu_helper.c index 7d08aae..4844f1e 100644 --- a/target-s390x/fpu_helper.c +++ b/target-s390x/fpu_helper.c @@ -495,28 +495,6 @@ uint32_t HELPER(cfxbr)(CPUS390XState *env, uint32_t r1, uint32_t f2, return set_cc_nz_f128(v2.q); } -/* load 32-bit FP zero */ -void HELPER(lzer)(CPUS390XState *env, uint32_t f1) -{ - env->fregs[f1].l.upper = float32_zero; -} - -/* load 64-bit FP zero */ -void HELPER(lzdr)(CPUS390XState *env, uint32_t f1) -{ - env->fregs[f1].d = float64_zero; -} - -/* load 128-bit FP zero */ -void HELPER(lzxr)(CPUS390XState *env, uint32_t f1) -{ - CPU_QuadU x; - - x.q = float64_to_float128(float64_zero, &env->fpu_status); - env->fregs[f1].ll = x.ll.upper; - env->fregs[f1 + 1].ll = x.ll.lower; -} - /* 32-bit FP multiply and add */ uint64_t HELPER(maeb)(CPUS390XState *env, uint64_t f1, uint64_t f2, uint64_t f3) diff --git a/target-s390x/helper.h b/target-s390x/helper.h index a7dcee9..348f4cd 100644 --- a/target-s390x/helper.h +++ b/target-s390x/helper.h @@ -73,9 +73,6 @@ DEF_HELPER_FLAGS_5(cxb, TCG_CALL_PURE, i32, env, i64, i64, i64, i64) DEF_HELPER_4(cgebr, i32, env, i32, i32, i32) DEF_HELPER_4(cgdbr, i32, env, i32, i32, i32) DEF_HELPER_4(cgxbr, i32, env, i32, i32, i32) -DEF_HELPER_2(lzer, void, env, i32) -DEF_HELPER_2(lzdr, void, env, i32) -DEF_HELPER_2(lzxr, void, env, i32) DEF_HELPER_4(cfebr, i32, env, i32, i32, i32) DEF_HELPER_4(cfdbr, i32, env, i32, i32, i32) DEF_HELPER_4(cfxbr, i32, env, i32, i32, i32) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 97c38f2..912c1fa 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -329,6 +329,10 @@ C(0xe31f, LRVH, RXY_a, Z, 0, m2_16u, new, r1_16, rev16, 0) C(0xe31e, LRV, RXY_a, Z, 0, m2_32u, new, r1_32, rev32, 0) C(0xe30f, LRVG, RXY_a, Z, 0, m2_64, r1, 0, rev64, 0) +/* LOAD ZERO */ + C(0xb374, LZER, RRE, Z, 0, 0, 0, e1, zero, 0) + C(0xb375, LZDR, RRE, Z, 0, 0, 0, f1, zero, 0) + C(0xb376, LZXR, RRE, Z, 0, 0, 0, x1, zero2, 0) /* LOAD LENGTHENED */ C(0xb304, LDEBR, RRE, Z, 0, e2, f1, 0, ldeb, 0) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 86b222a..3c69079 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -1381,21 +1381,6 @@ static void disas_b3(DisasContext *s, int op, int m3, int r1, int r2) tcg_temp_free_i32(tmp32_2); switch (op) { - case 0x74: /* LZER R1 [RRE] */ - tmp32_1 = tcg_const_i32(r1); - gen_helper_lzer(cpu_env, tmp32_1); - tcg_temp_free_i32(tmp32_1); - break; - case 0x75: /* LZDR R1 [RRE] */ - tmp32_1 = tcg_const_i32(r1); - gen_helper_lzdr(cpu_env, tmp32_1); - tcg_temp_free_i32(tmp32_1); - break; - case 0x76: /* LZXR R1 [RRE] */ - tmp32_1 = tcg_const_i32(r1); - gen_helper_lzxr(cpu_env, tmp32_1); - tcg_temp_free_i32(tmp32_1); - break; case 0x84: /* SFPC R1 [RRE] */ tmp32_1 = load_reg32(r1); tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUS390XState, fpc)); @@ -3232,6 +3217,20 @@ static ExitStatus op_xori(DisasContext *s, DisasOps *o) return NO_EXIT; } +static ExitStatus op_zero(DisasContext *s, DisasOps *o) +{ + o->out = tcg_const_i64(0); + return NO_EXIT; +} + +static ExitStatus op_zero2(DisasContext *s, DisasOps *o) +{ + o->out = tcg_const_i64(0); + o->out2 = o->out; + o->g_out2 = true; + return NO_EXIT; +} + /* ====================================================================== */ /* The "Cc OUTput" generators. Given the generated output (and in some cases the original inputs), update the various cc data structures in order to