From patchwork Sun Sep 9 21:05:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 182654 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2F49C2C009F for ; Mon, 10 Sep 2012 07:11:54 +1000 (EST) Received: from localhost ([::1]:34888 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAonI-00068c-82 for incoming@patchwork.ozlabs.org; Sun, 09 Sep 2012 17:11:52 -0400 Received: from eggs.gnu.org ([208.118.235.92]:56788) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAoiy-00089n-Iz for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TAoix-00066S-AD for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:24 -0400 Received: from mail-pz0-f45.google.com ([209.85.210.45]:63059) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAoix-0005pO-43 for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:23 -0400 Received: by mail-pz0-f45.google.com with SMTP id n15so968311dad.4 for ; Sun, 09 Sep 2012 14:07:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=xapHu9k8C7zRu6+gVeK6u58DdL856F5sHbs6s1SVEuQ=; b=VvOqqT/MhFEcH+LXl0d2/1EpojV7zhhpQKSmavyGkKpu3DDIRpn1TUh9Ja/khsuGK/ IR26pXqoIwVtXilXQ98lyqDP2W6MyOdEKs9qNFyMnj2U7cF8RShkmG9heGQ8yzNODL5L w9PyqCACU3kyYpd2dpOePS5Lhoe0nwiVC3FwpYmuM1hBaJM5HJd+qlbKW2dEPkEmj/i2 Es1uCmmxSBu/GX0gL3D3s9e5WeaSFrYtgbOuLyxcRe6O3DlC0LzBrWNP4ZufQ2ByNr/P 7SjIXp9WO7uVulBFeQJHWmvGSbtPe8Blb9tTrL6nebU4zpuUcdzM31PYiGyffxXO/2Pv Z5Tw== Received: by 10.68.223.3 with SMTP id qq3mr2032768pbc.88.1347224842850; Sun, 09 Sep 2012 14:07:22 -0700 (PDT) Received: from anchor.twiddle.home ([173.160.232.49]) by mx.google.com with ESMTPS id tw5sm662053pbc.48.2012.09.09.14.07.22 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 09 Sep 2012 14:07:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 9 Sep 2012 14:05:15 -0700 Message-Id: <1347224784-19472-58-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1347224784-19472-1-git-send-email-rth@twiddle.net> References: <1347224784-19472-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.210.45 Cc: Alexander Graf Subject: [Qemu-devel] [PATCH 057/126] target-s390: Convert LRA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Note that truncating the store to r1 based on PSW_MASK_64 is incorrect. We always modify the entire register. Signed-off-by: Richard Henderson --- target-s390x/helper.h | 2 +- target-s390x/insn-data.def | 4 ++++ target-s390x/mem_helper.c | 13 +++---------- target-s390x/translate.c | 20 +++++++++----------- 4 files changed, 17 insertions(+), 22 deletions(-) diff --git a/target-s390x/helper.h b/target-s390x/helper.h index 93931e4..4a041cb 100644 --- a/target-s390x/helper.h +++ b/target-s390x/helper.h @@ -140,7 +140,7 @@ DEF_HELPER_4(sigp, i32, env, i64, i32, i64) DEF_HELPER_2(sacf, void, env, i64) DEF_HELPER_FLAGS_3(ipte, TCG_CALL_CONST, void, env, i64, i64) DEF_HELPER_FLAGS_1(ptlb, TCG_CALL_CONST, void, env) -DEF_HELPER_3(lra, i32, env, i64, i32) +DEF_HELPER_2(lra, i64, env, i64) DEF_HELPER_3(stura, void, env, i64, i32) DEF_HELPER_3(cksm, void, env, i32, i32) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 301e509..a078cc5 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -461,6 +461,10 @@ C(0x8300, DIAG, RX_a, Z, 0, 0, 0, 0, diag, 0) /* LOAD PSW */ C(0x8200, LPSW, S, Z, 0, a2, 0, 0, lpsw, 0) +/* LOAD REAL ADDRESS */ + C(0xb100, LRA, RX_a, Z, 0, a2, r1, 0, lra, 0) + C(0xe313, LRAY, RXY_a, LD, 0, a2, r1, 0, lra, 0) + C(0xe303, LRAG, RXY_a, Z, 0, a2, r1, 0, lra, 0) /* MOVE TO PRIMARY */ C(0xda00, MVCP, SS_d, Z, la1, a2, 0, 0, mvcp, 0) /* MOVE TO SECONDARY */ diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c index b868346..961f748 100644 --- a/target-s390x/mem_helper.c +++ b/target-s390x/mem_helper.c @@ -1133,7 +1133,7 @@ void HELPER(stura)(CPUS390XState *env, uint64_t addr, uint32_t v1) } /* load real address */ -uint32_t HELPER(lra)(CPUS390XState *env, uint64_t addr, uint32_t r1) +uint64_t HELPER(lra)(CPUS390XState *env, uint64_t addr) { uint32_t cc = 0; int old_exc = env->exception_index; @@ -1157,14 +1157,7 @@ uint32_t HELPER(lra)(CPUS390XState *env, uint64_t addr, uint32_t r1) } env->exception_index = old_exc; - if (!(env->psw.mask & PSW_MASK_64)) { - env->regs[r1] = (env->regs[r1] & 0xffffffff00000000ULL) | - (ret & 0xffffffffULL); - } else { - env->regs[r1] = ret; - } - - return cc; + env->cc_op = cc; + return ret; } - #endif diff --git a/target-s390x/translate.c b/target-s390x/translate.c index c8ab897..1829b25 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -2015,17 +2015,6 @@ static void disas_s390_insn(DisasContext *s) tcg_temp_free_i64(tmp2); tcg_temp_free_i32(tmp32_1); break; - case 0xb1: /* LRA R1,D2(X2, B2) [RX] */ - check_privileged(s); - insn = ld_code4(s->pc); - tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); - tmp32_1 = tcg_const_i32(r1); - potential_page_fault(s); - gen_helper_lra(cc_op, cpu_env, tmp, tmp32_1); - set_cc_static(s); - tcg_temp_free_i64(tmp); - tcg_temp_free_i32(tmp32_1); - break; #endif case 0xb2: insn = ld_code4(s->pc); @@ -2887,6 +2876,15 @@ static ExitStatus op_ld64(DisasContext *s, DisasOps *o) } #ifndef CONFIG_USER_ONLY +static ExitStatus op_lra(DisasContext *s, DisasOps *o) +{ + check_privileged(s); + potential_page_fault(s); + gen_helper_lra(o->out, cpu_env, o->in2); + set_cc_static(s); + return NO_EXIT; +} + static ExitStatus op_lpsw(DisasContext *s, DisasOps *o) { TCGv_i64 t1, t2;