From patchwork Sun Sep 9 21:05:13 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 182739 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id F25832C0086 for ; Mon, 10 Sep 2012 09:12:27 +1000 (EST) Received: from localhost ([::1]:56391 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAolD-0002Uf-BL for incoming@patchwork.ozlabs.org; Sun, 09 Sep 2012 17:09:43 -0400 Received: from eggs.gnu.org ([208.118.235.92]:56768) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAoix-00086J-B2 for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TAoiv-000660-JM for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:23 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:59699) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAoiv-0005pQ-DA for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:21 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp12so291958pbb.4 for ; Sun, 09 Sep 2012 14:07:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=pS19fK5e/g7ujCk1gcjL+d3zxLMjQRuw7/Mq5JfkT+Y=; b=zTfpoCMnVq0RfKmVnvIpkramHafXbwWTnzgO+hC5wVmGhw5nWjY5Xii+y2Z8xgAP1b 0MzrAFgdKzv33VTutkjfCNEZUl4FJDvWd/X5uFXKg46GH1u30xILZ+HXm5uzu8rQ8nJm OF9vKUMsK7YZBJ0hwO0SYXiSjuYh0qBDGxbJv60yvsDXYDJwYQ2iwth1+heb9usMPvQG lYplvQpRKbRCs+eIX6/DjXtii7hyMKW4w0lPib2w0KyVdPrNTTbeiw71ZG3KX2MvThmR 5wKaGbOwR7Zr8dnWqlFtWoTbEdMLqtWdnDvrTSMzVivYtP4PWqpfIJALItKe09jeXh0d mS3A== Received: by 10.68.218.196 with SMTP id pi4mr2027442pbc.128.1347224841171; Sun, 09 Sep 2012 14:07:21 -0700 (PDT) Received: from anchor.twiddle.home ([173.160.232.49]) by mx.google.com with ESMTPS id tw5sm662053pbc.48.2012.09.09.14.07.20 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 09 Sep 2012 14:07:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 9 Sep 2012 14:05:13 -0700 Message-Id: <1347224784-19472-56-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1347224784-19472-1-git-send-email-rth@twiddle.net> References: <1347224784-19472-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Alexander Graf Subject: [Qemu-devel] [PATCH 055/126] target-s390: Convert CLC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-s390x/insn-data.def | 1 + target-s390x/translate.c | 107 ++++++++++++++------------------------------- 2 files changed, 35 insertions(+), 73 deletions(-) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index f7941d8..fa0711f 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -119,6 +119,7 @@ C(0xb931, CLGFR, RRE, Z, r1, r2_32u, 0, 0, 0, cmpu64) C(0xe321, CLG, RXY_a, Z, r1, m2_64, 0, 0, 0, cmpu64) C(0xe331, CLGF, RXY_a, Z, r1, m2_32u, 0, 0, 0, cmpu64) + C(0xd500, CLC, SS_a, Z, la1, a2, 0, 0, clc, 0) /* COMPARE LOGICAL IMMEDIATE */ C(0xc20f, CLFI, RIL_a, EI, r1, i2, 0, 0, 0, cmpu32) C(0xc20e, CLGFI, RIL_a, EI, r1, i2_32u, 0, 0, 0, cmpu64) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 45b8c3a..b3f79bd 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -1010,67 +1010,6 @@ static void free_compare(DisasCompare *c) } } -static void gen_op_clc(DisasContext *s, int l, TCGv_i64 s1, TCGv_i64 s2) -{ - TCGv_i64 tmp; - TCGv_i64 tmp2; - TCGv_i32 vl; - - /* check for simple 32bit or 64bit match */ - switch (l) { - case 0: - tmp = tcg_temp_new_i64(); - tmp2 = tcg_temp_new_i64(); - - tcg_gen_qemu_ld8u(tmp, s1, get_mem_index(s)); - tcg_gen_qemu_ld8u(tmp2, s2, get_mem_index(s)); - cmp_u64(s, tmp, tmp2); - - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tmp2); - return; - case 1: - tmp = tcg_temp_new_i64(); - tmp2 = tcg_temp_new_i64(); - - tcg_gen_qemu_ld16u(tmp, s1, get_mem_index(s)); - tcg_gen_qemu_ld16u(tmp2, s2, get_mem_index(s)); - cmp_u64(s, tmp, tmp2); - - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tmp2); - return; - case 3: - tmp = tcg_temp_new_i64(); - tmp2 = tcg_temp_new_i64(); - - tcg_gen_qemu_ld32u(tmp, s1, get_mem_index(s)); - tcg_gen_qemu_ld32u(tmp2, s2, get_mem_index(s)); - cmp_u64(s, tmp, tmp2); - - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tmp2); - return; - case 7: - tmp = tcg_temp_new_i64(); - tmp2 = tcg_temp_new_i64(); - - tcg_gen_qemu_ld64(tmp, s1, get_mem_index(s)); - tcg_gen_qemu_ld64(tmp2, s2, get_mem_index(s)); - cmp_u64(s, tmp, tmp2); - - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tmp2); - return; - } - - potential_page_fault(s); - vl = tcg_const_i32(l); - gen_helper_clc(cc_op, cpu_env, vl, s1, s2); - tcg_temp_free_i32(vl); - set_cc_static(s); -} - static void disas_e3(DisasContext* s, int op, int r1, int x2, int b2, int d2) { TCGv_i64 addr, tmp2; @@ -2193,18 +2132,6 @@ static void disas_s390_insn(DisasContext *s) tcg_temp_free_i32(tmp32_1); tcg_temp_free_i32(tmp32_2); break; - case 0xd5: /* CLC D1(L,B1),D2(B2) [SS] */ - insn = ld_code6(s->pc); - b1 = (insn >> 28) & 0xf; - b2 = (insn >> 12) & 0xf; - d1 = (insn >> 16) & 0xfff; - d2 = insn & 0xfff; - tmp = get_address(s, 0, b1, d1); - tmp2 = get_address(s, 0, b2, d2); - gen_op_clc(s, (insn >> 32) & 0xff, tmp, tmp2); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tmp2); - break; #ifndef CONFIG_USER_ONLY case 0xda: /* MVCP D1(R1,B1),D2(B2),R3 [SS] */ case 0xdb: /* MVCS D1(R1,B1),D2(B2),R3 [SS] */ @@ -2746,6 +2673,40 @@ static ExitStatus op_bct64(DisasContext *s, DisasOps *o) return help_branch(s, &c, is_imm, imm, o->in2); } +static ExitStatus op_clc(DisasContext *s, DisasOps *o) +{ + int l = get_field(s->fields, l1); + TCGv_i32 vl; + + switch (l + 1) { + case 1: + tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s)); + tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s)); + break; + case 2: + tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s)); + tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s)); + break; + case 4: + tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s)); + tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s)); + break; + case 8: + tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s)); + tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s)); + break; + default: + potential_page_fault(s); + vl = tcg_const_i32(l); + gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2); + tcg_temp_free_i32(vl); + set_cc_static(s); + return NO_EXIT; + } + gen_op_update2_cc_i64(s, CC_OP_LTUGTU_64, cc_src, cc_dst); + return NO_EXIT; +} + static ExitStatus op_clcle(DisasContext *s, DisasOps *o) { TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));