From patchwork Sun Sep 9 21:05:12 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 182704 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1A5432C00A0 for ; Mon, 10 Sep 2012 08:42:04 +1000 (EST) Received: from localhost ([::1]:56347 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAol7-0002Ta-8T for incoming@patchwork.ozlabs.org; Sun, 09 Sep 2012 17:09:37 -0400 Received: from eggs.gnu.org ([208.118.235.92]:56755) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAoiw-000833-58 for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TAoiu-00065W-OG for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:22 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:63857) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAoiu-0005xl-IB for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:20 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp12so292285pbb.4 for ; Sun, 09 Sep 2012 14:07:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=b1n976wMzetYcgNFYn0xGAmUacRs98e8F8LsM+t4jJg=; b=XKqeRJgKg1oWqz9vpXoGWxw5nTMvyrLdTCmwIiqOx2mPwvKNf20nHcPT7BzCh0dS2U LcRs1cz+yxzhcT1vRg6KPnbTP7CQ+3MYgzvookCyhNVRbpjfRyRKGO+s6uG+1iFq6w6d RD+J4lwD8ot7LuTr9JxwRp9wGeAZt/tEdL4pg9NTwfYY7ltFPWE1Gx4hgKWLMBnVnPNM v2MyfVFZcse1xx7hUafTHpMB0WPoDLMBjSAaTFmcUFGjfMbm5X4xdOlAL46+OSu7OBkd wamdrWoenVs9tKV/28Axjh54c5zn9+vGx7+97F0FKaIUJw9Uej5dJHuLcvNIpCPOlHJS PNGA== Received: by 10.66.79.195 with SMTP id l3mr18160534pax.33.1347224840302; Sun, 09 Sep 2012 14:07:20 -0700 (PDT) Received: from anchor.twiddle.home ([173.160.232.49]) by mx.google.com with ESMTPS id tw5sm662053pbc.48.2012.09.09.14.07.19 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 09 Sep 2012 14:07:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 9 Sep 2012 14:05:12 -0700 Message-Id: <1347224784-19472-55-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1347224784-19472-1-git-send-email-rth@twiddle.net> References: <1347224784-19472-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Alexander Graf Subject: [Qemu-devel] [PATCH 054/126] target-s390: Convert NC, XC, OC, TR, UNPK X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-s390x/insn-data.def | 11 ++++++ target-s390x/translate.c | 88 ++++++++++++++++++++++++++-------------------- 2 files changed, 61 insertions(+), 38 deletions(-) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index aa70715..f7941d8 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -54,6 +54,7 @@ C(0xb980, NGR, RRE, Z, r1, r2, r1, 0, and, nz64) C(0xb9e4, NGRK, RRF_a, DO, r2, r3, r1, 0, and, nz64) C(0xe380, NG, RXY_a, Z, r1, m2_64, r1, 0, and, nz64) + C(0xd400, NC, SS_a, Z, la1, a2, 0, 0, nc, 0) /* AND IMMEDIATE */ D(0xc00a, NIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, andi, 0, 0x2020) D(0xc00b, NILF, RIL_a, EI, r1_o, i2_32u, r1, 0, andi, 0, 0x2000) @@ -161,6 +162,7 @@ C(0xb982, XGR, RRE, Z, r1, r2, r1, 0, xor, nz64) C(0xb9e7, XGRK, RRF_a, DO, r2, r3, r1, 0, xor, nz64) C(0xe382, XG, RXY_a, Z, r1, m2_64, r1, 0, xor, nz64) + C(0xd700, XC, SS_a, Z, la1, a2, 0, 0, xc, 0) /* EXCLUSIVE OR IMMEDIATE */ D(0xc006, XIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, xori, 0, 0x2020) D(0xc007, XILF, RIL_a, EI, r1_o, i2_32u, r1, 0, xori, 0, 0x2000) @@ -332,6 +334,7 @@ C(0xb981, OGR, RRE, Z, r1, r2, r1, 0, or, nz64) C(0xb9e6, OGRK, RRF_a, DO, r2, r3, r1, 0, or, nz64) C(0xe381, OG, RXY_a, Z, r1, m2_64, r1, 0, or, nz64) + C(0xd600, OC, SS_a, Z, la1, a2, 0, 0, oc, 0) /* OR IMMEDIATE */ D(0xc00c, OIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, ori, 0, 0x2020) D(0xc00d, OILF, RIL_a, EI, r1_o, i2_32u, r1, 0, ori, 0, 0x2000) @@ -444,6 +447,14 @@ D(0xa700, TMLH, RI_a, Z, r1_o, i2_16u_shl, 0, 0, 0, tm64, 16) D(0xa701, TMLL, RI_a, Z, r1_o, i2_16u_shl, 0, 0, 0, tm64, 0) +/* TRANSLATE */ + C(0xdc00, TR, SS_a, Z, la1, a2, 0, 0, tr, 0) + +/* UNPACK */ + /* Really format SS_b, but we pack both lengths into one argument + for the helper call, so we might as well leave one 8-bit field. */ + C(0xf300, UNPK, SS_a, Z, la1, a2, 0, 0, unpk, 0) + #ifndef CONFIG_USER_ONLY /* DIAGNOSE (KVM hypercall) */ C(0x8300, DIAG, RX_a, Z, 0, 0, 0, 0, diag, 0) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index f463525..45b8c3a 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -2056,7 +2056,6 @@ static void disas_s390_insn(DisasContext *s) unsigned char opc; uint64_t insn; int op, r1, r2, r3, d1, d2, x2, b1, b2, r1b; - TCGv_i32 vl; opc = cpu_ldub_code(cpu_single_env, s->pc); LOG_DISAS("opc 0x%x\n", opc); @@ -2194,51 +2193,15 @@ static void disas_s390_insn(DisasContext *s) tcg_temp_free_i32(tmp32_1); tcg_temp_free_i32(tmp32_2); break; - case 0xd4: /* NC D1(L,B1),D2(B2) [SS] */ case 0xd5: /* CLC D1(L,B1),D2(B2) [SS] */ - case 0xd6: /* OC D1(L,B1),D2(B2) [SS] */ - case 0xd7: /* XC D1(L,B1),D2(B2) [SS] */ - case 0xdc: /* TR D1(L,B1),D2(B2) [SS] */ - case 0xf3: /* UNPK D1(L1,B1),D2(L2,B2) [SS] */ insn = ld_code6(s->pc); - vl = tcg_const_i32((insn >> 32) & 0xff); b1 = (insn >> 28) & 0xf; b2 = (insn >> 12) & 0xf; d1 = (insn >> 16) & 0xfff; d2 = insn & 0xfff; tmp = get_address(s, 0, b1, d1); tmp2 = get_address(s, 0, b2, d2); - switch (opc) { - case 0xd4: - potential_page_fault(s); - gen_helper_nc(cc_op, cpu_env, vl, tmp, tmp2); - set_cc_static(s); - break; - case 0xd5: - gen_op_clc(s, (insn >> 32) & 0xff, tmp, tmp2); - break; - case 0xd6: - potential_page_fault(s); - gen_helper_oc(cc_op, cpu_env, vl, tmp, tmp2); - set_cc_static(s); - break; - case 0xd7: - potential_page_fault(s); - gen_helper_xc(cc_op, cpu_env, vl, tmp, tmp2); - set_cc_static(s); - break; - case 0xdc: - potential_page_fault(s); - gen_helper_tr(cpu_env, vl, tmp, tmp2); - set_cc_static(s); - break; - case 0xf3: - potential_page_fault(s); - gen_helper_unpk(cpu_env, vl, tmp, tmp2); - break; - default: - tcg_abort(); - } + gen_op_clc(s, (insn >> 32) & 0xff, tmp, tmp2); tcg_temp_free_i64(tmp); tcg_temp_free_i64(tmp2); break; @@ -3141,12 +3104,32 @@ static ExitStatus op_nabs(DisasContext *s, DisasOps *o) return NO_EXIT; } +static ExitStatus op_nc(DisasContext *s, DisasOps *o) +{ + TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1)); + potential_page_fault(s); + gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2); + tcg_temp_free_i32(l); + set_cc_static(s); + return NO_EXIT; +} + static ExitStatus op_neg(DisasContext *s, DisasOps *o) { tcg_gen_neg_i64(o->out, o->in2); return NO_EXIT; } +static ExitStatus op_oc(DisasContext *s, DisasOps *o) +{ + TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1)); + potential_page_fault(s); + gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2); + tcg_temp_free_i32(l); + set_cc_static(s); + return NO_EXIT; +} + static ExitStatus op_or(DisasContext *s, DisasOps *o) { tcg_gen_or_i64(o->out, o->in1, o->in2); @@ -3366,6 +3349,35 @@ static ExitStatus op_svc(DisasContext *s, DisasOps *o) return EXIT_NORETURN; } +static ExitStatus op_tr(DisasContext *s, DisasOps *o) +{ + TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1)); + potential_page_fault(s); + gen_helper_tr(cpu_env, l, o->addr1, o->in2); + tcg_temp_free_i32(l); + set_cc_static(s); + return NO_EXIT; +} + +static ExitStatus op_unpk(DisasContext *s, DisasOps *o) +{ + TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1)); + potential_page_fault(s); + gen_helper_unpk(cpu_env, l, o->addr1, o->in2); + tcg_temp_free_i32(l); + return NO_EXIT; +} + +static ExitStatus op_xc(DisasContext *s, DisasOps *o) +{ + TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1)); + potential_page_fault(s); + gen_helper_xc(cc_op, cpu_env, l, o->addr1, o->in2); + tcg_temp_free_i32(l); + set_cc_static(s); + return NO_EXIT; +} + static ExitStatus op_xor(DisasContext *s, DisasOps *o) { tcg_gen_xor_i64(o->out, o->in1, o->in2);