From patchwork Sun Sep 9 21:05:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 182653 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 5AE232C0079 for ; Mon, 10 Sep 2012 07:11:31 +1000 (EST) Received: from localhost ([::1]:32865 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAomv-00053D-DR for incoming@patchwork.ozlabs.org; Sun, 09 Sep 2012 17:11:29 -0400 Received: from eggs.gnu.org ([208.118.235.92]:56565) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAoil-0007nO-GJ for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TAoik-00061r-BU for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:11 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:59699) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAoij-0005pQ-Tr for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:10 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp12so291958pbb.4 for ; Sun, 09 Sep 2012 14:07:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=iKhA59uLIs/azujVZDMifUjZ6Zal3wGhByGXN8TMMB4=; b=0P/MOsodA/93Lgiki/pF7Me4Q9z5S3q+/VOjKakR98L+G5M+RhpraCTv3leiJvvs27 V9gEA4U+Fn8p358cWxoei0KqqMPdqwsGLvM+hA6ZFxcvFUmw0ysfu4y1BHnhxlusQUSB 4LoCA76q1hWeiEw6L8rVUJs7X4vsMj9L1eveByulaCjuAP1A3ac9V8sWy/eFxlF0yNqA JiNPgXFXzD5TKrPq+aRWCw5R8AFk4dW75SGYmzimHKd3QSF/5dDX8j8xG5ypFGe24yfy nOZtTh/J9Y3POt3XFOvc0J9gIf84LSLusjUEB4nittDOh6ZBGOdWth9QXff7D5ypM3HD oaWA== Received: by 10.66.90.1 with SMTP id bs1mr18155379pab.13.1347224829633; Sun, 09 Sep 2012 14:07:09 -0700 (PDT) Received: from anchor.twiddle.home ([173.160.232.49]) by mx.google.com with ESMTPS id tw5sm662053pbc.48.2012.09.09.14.07.08 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 09 Sep 2012 14:07:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 9 Sep 2012 14:05:00 -0700 Message-Id: <1347224784-19472-43-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1347224784-19472-1-git-send-email-rth@twiddle.net> References: <1347224784-19472-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Alexander Graf Subject: [Qemu-devel] [PATCH 042/126] target-s390: Convert SET SYSTEM MASK X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-s390x/insn-data.def | 2 ++ target-s390x/translate.c | 25 +++++++++---------------- 2 files changed, 11 insertions(+), 16 deletions(-) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 9d26370..7af3ba3 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -383,4 +383,6 @@ /* We only do 64-bit, so accept this as a no-op. Let SAM24 and SAM31 signal illegal instruction. */ C(0x010e, SAM64, E, Z, 0, 0, 0, 0, 0, 0) +/* SET SYSTEM MASK */ + C(0x8000, SSM, S, Z, 0, m2_8u, 0, 0, ssm, 0) #endif /* CONFIG_USER_ONLY */ diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 11feffd..deb5cb9 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -2349,22 +2349,6 @@ static void disas_s390_insn(DisasContext *s) switch (opc) { #ifndef CONFIG_USER_ONLY - case 0x80: /* SSM D2(B2) [S] */ - /* Set System Mask */ - check_privileged(s); - insn = ld_code4(s->pc); - decode_rs(s, insn, &r1, &r3, &b2, &d2); - tmp = get_address(s, 0, b2, d2); - tmp2 = tcg_temp_new_i64(); - tmp3 = tcg_temp_new_i64(); - tcg_gen_andi_i64(tmp3, psw_mask, ~0xff00000000000000ULL); - tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s)); - tcg_gen_shli_i64(tmp2, tmp2, 56); - tcg_gen_or_i64(psw_mask, tmp3, tmp2); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tmp2); - tcg_temp_free_i64(tmp3); - break; case 0x82: /* LPSW D2(B2) [S] */ /* Load PSW */ check_privileged(s); @@ -3554,6 +3538,15 @@ static ExitStatus op_ori(DisasContext *s, DisasOps *o) return NO_EXIT; } +#ifndef CONFIG_USER_ONLY +static ExitStatus op_ssm(DisasContext *s, DisasOps *o) +{ + check_privileged(s); + tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, 56, 8); + return NO_EXIT; +} +#endif + static ExitStatus op_st8(DisasContext *s, DisasOps *o) { tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));