From patchwork Sun Sep 9 21:04:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 182696 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 7582E2C009D for ; Mon, 10 Sep 2012 08:36:11 +1000 (EST) Received: from localhost ([::1]:59742 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAomO-0004Kp-Pm for incoming@patchwork.ozlabs.org; Sun, 09 Sep 2012 17:10:56 -0400 Received: from eggs.gnu.org ([208.118.235.92]:56469) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAoif-0007WI-Tp for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TAoie-000602-OS for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:05 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:59699) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAoie-0005pQ-I9 for qemu-devel@nongnu.org; Sun, 09 Sep 2012 17:07:04 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp12so291958pbb.4 for ; Sun, 09 Sep 2012 14:07:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=Tndcger8xiCv1kQ6tQaHyD5S/Atmc9JWm2bmtBPNAGI=; b=SSz5PzAc/7jlMLZyok90xvj6m4q9PPegCFl5OZiI6d1G7QVMQ2WlwkBcoGvIgQIFqB 8PCnAQcBZKNc4qRZOmhYS52OC+3OlHdEczv3ame9wWOtp0/4X7yexSFYPE5H8WlyAeu6 1NR6sHk4cKqemCpsbCBbVnBcIr2w/4oXc56Bokjkl9coAO7gyfKPBaxHGYfDWpczJ2Cg dF9B8pl7lTSbnDQKqkTJ6j3JqsRMFLKPvVyzfRGB5g0kWOTNfS9CXeohp+NvfV8Eq1h6 /+Js7HoVAf0Gew+RZM9YOrBBwbdS1OKVVYAPSKeFsrbccZKsF3LyKC0VROv1f543wTlR tERQ== Received: by 10.68.200.8 with SMTP id jo8mr2032604pbc.148.1347224824305; Sun, 09 Sep 2012 14:07:04 -0700 (PDT) Received: from anchor.twiddle.home ([173.160.232.49]) by mx.google.com with ESMTPS id tw5sm662053pbc.48.2012.09.09.14.07.03 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 09 Sep 2012 14:07:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 9 Sep 2012 14:04:54 -0700 Message-Id: <1347224784-19472-37-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1347224784-19472-1-git-send-email-rth@twiddle.net> References: <1347224784-19472-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Alexander Graf Subject: [Qemu-devel] [PATCH 036/126] target-s390: Convert INSERT CHARACTER X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-s390x/insn-data.def | 3 +++ target-s390x/translate.c | 35 +++++++++++++---------------------- 2 files changed, 16 insertions(+), 22 deletions(-) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 02e9cc0..7fff688 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -157,6 +157,9 @@ D(0xc006, XIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, xori, 0, 0x2020) D(0xc007, XILF, RIL_a, EI, r1_o, i2_32u, r1, 0, xori, 0, 0x2000) +/* INSERT CHARACTER */ + C(0x4300, IC, RX_a, Z, 0, m2_8u, 0, r1_8, mov2, 0) + C(0xe373, ICY, RXY_a, LD, 0, m2_8u, 0, r1_8, mov2, 0) /* INSERT IMMEDIATE */ D(0xc008, IIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, insi, 0, 0x2020) D(0xc009, IILF, RIL_a, EI, r1_o, i2_32u, r1, 0, insi, 0, 0x2000) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index c36ad44..4f7731a 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -281,12 +281,6 @@ static inline void store_reg16(int reg, TCGv_i32 v) #endif } -static inline void store_reg8(int reg, TCGv_i64 v) -{ - /* 8 bit register writes keep the upper bytes */ - tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 8); -} - static inline void store_freg32(int reg, TCGv_i32 v) { /* 32 bit register writes keep the lower half */ @@ -1241,7 +1235,7 @@ static void gen_op_clc(DisasContext *s, int l, TCGv_i64 s1, TCGv_i64 s2) static void disas_e3(DisasContext* s, int op, int r1, int x2, int b2, int d2) { - TCGv_i64 addr, tmp2, tmp3; + TCGv_i64 addr, tmp2; TCGv_i32 tmp32_1; LOG_DISAS("disas_e3: op 0x%x r1 %d x2 %d b2 %d d2 %d\n", @@ -1291,12 +1285,6 @@ static void disas_e3(DisasContext* s, int op, int r1, int x2, int b2, int d2) tcg_gen_qemu_st32(tmp2, addr, get_mem_index(s)); tcg_temp_free_i64(tmp2); break; - case 0x73: /* ICY R1,D2(X2,B2) [RXY] */ - tmp3 = tcg_temp_new_i64(); - tcg_gen_qemu_ld8u(tmp3, addr, get_mem_index(s)); - store_reg8(r1, tmp3); - tcg_temp_free_i64(tmp3); - break; default: LOG_DISAS("illegal e3 operation 0x%x\n", op); gen_illegal_opcode(s); @@ -2376,15 +2364,6 @@ static void disas_s390_insn(DisasContext *s) LOG_DISAS("opc 0x%x\n", opc); switch (opc) { - case 0x43: /* IC R1,D2(X2,B2) [RX] */ - insn = ld_code4(s->pc); - tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); - tmp2 = tcg_temp_new_i64(); - tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s)); - store_reg8(r1, tmp2); - tcg_temp_free_i64(tmp); - tcg_temp_free_i64(tmp2); - break; case 0x44: /* EX R1,D2(X2,B2) [RX] */ insn = ld_code4(s->pc); tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2); @@ -3869,6 +3848,12 @@ static void wout_r1(DisasContext *s, DisasFields *f, DisasOps *o) store_reg(get_field(f, r1), o->out); } +static void wout_r1_8(DisasContext *s, DisasFields *f, DisasOps *o) +{ + int r1 = get_field(f, r1); + tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8); +} + static void wout_r1_32(DisasContext *s, DisasFields *f, DisasOps *o) { store_reg32_i64(get_field(f, r1), o->out); @@ -4127,6 +4112,12 @@ static void in2_ri2(DisasContext *s, DisasFields *f, DisasOps *o) o->in2 = tcg_const_i64(s->pc + (int64_t)get_field(f, i2) * 2); } +static void in2_m2_8u(DisasContext *s, DisasFields *f, DisasOps *o) +{ + in2_a2(s, f, o); + tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s)); +} + static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o) { in2_a2(s, f, o);