From patchwork Sun Sep 9 16:04:36 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 182633 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3CCBD2C0089 for ; Mon, 10 Sep 2012 02:46:21 +1000 (EST) Received: from localhost ([::1]:56141 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAk19-0004jR-F1 for incoming@patchwork.ozlabs.org; Sun, 09 Sep 2012 12:05:51 -0400 Received: from eggs.gnu.org ([208.118.235.92]:36326) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAk0l-0003vN-8q for qemu-devel@nongnu.org; Sun, 09 Sep 2012 12:05:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TAk0j-00089H-V0 for qemu-devel@nongnu.org; Sun, 09 Sep 2012 12:05:27 -0400 Received: from mail-lb0-f173.google.com ([209.85.217.173]:55864) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAk0j-0007ZU-Nk for qemu-devel@nongnu.org; Sun, 09 Sep 2012 12:05:25 -0400 Received: by mail-lb0-f173.google.com with SMTP id gm13so650430lbb.4 for ; Sun, 09 Sep 2012 09:05:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=R5dO5jOKlB2aKvDF2LsIcjobuVbTJo6OBI5TmTt2lzY=; b=dk+EDFOvnOZuZyyQ49GCvQz7SSSEI/8/lZdTUxrEPtEIMFSF5IhDf1XYgXBn3/pQdV XbfF2tWwbolp24ckBd3L14PxnjJsF0Lio0Rsi97mbGqjVub+w2g8hcsjNPgURNnjnJvs I7nudl3NTMA9hk4xZVMFBjUtDfEW778I5qJp6QrIJohff1L2YolZ62BzMsB0pRTb54Gu 42sNVFKa3HignKHDP8kxUYCgtkQuDfekN/KyA7qXu91culpnFHnEoS1cKsKUQa/yGGuD 7bG+rlynU1xqt0B/yUdFws+J/mj85ZxQ/Ufm7LYGFdZxnI+xU1FQKYIj39wV6KU8rg+P Bg1g== Received: by 10.152.147.130 with SMTP id tk2mr10142761lab.4.1347206725297; Sun, 09 Sep 2012 09:05:25 -0700 (PDT) Received: from octofox.metropolis ([188.134.19.124]) by mx.google.com with ESMTPS id in6sm8995530lab.1.2012.09.09.09.05.20 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 09 Sep 2012 09:05:23 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Sun, 9 Sep 2012 20:04:36 +0400 Message-Id: <1347206679-428-8-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 1.7.7.6 In-Reply-To: <1347206679-428-1-git-send-email-jcmvbkbc@gmail.com> References: <1347206679-428-1-git-send-email-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.217.173 Cc: Blue Swirl , Peter Maydell , Max Filippov Subject: [Qemu-devel] [PATCH v2 07/10] target-xtensa: implement FP0 arithmetic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org These are FP arithmetic opcodes. See ISA, 4.3.10 for more details. Signed-off-by: Max Filippov --- target-xtensa/helper.h | 7 +++++ target-xtensa/op_helper.c | 37 +++++++++++++++++++++++++++ target-xtensa/translate.c | 61 ++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 104 insertions(+), 1 deletions(-) diff --git a/target-xtensa/helper.h b/target-xtensa/helper.h index 1662552..4e6e417 100644 --- a/target-xtensa/helper.h +++ b/target-xtensa/helper.h @@ -37,5 +37,12 @@ DEF_HELPER_3(wsr_dbreaka, void, env, i32, i32) DEF_HELPER_3(wsr_dbreakc, void, env, i32, i32) DEF_HELPER_2(wur_fcr, void, env, i32) +DEF_HELPER_FLAGS_1(abs_s, TCG_CALL_CONST | TCG_CALL_PURE, f32, f32) +DEF_HELPER_FLAGS_1(neg_s, TCG_CALL_CONST | TCG_CALL_PURE, f32, f32) +DEF_HELPER_3(add_s, f32, env, f32, f32) +DEF_HELPER_3(sub_s, f32, env, f32, f32) +DEF_HELPER_3(mul_s, f32, env, f32, f32) +DEF_HELPER_4(madd_s, f32, env, f32, f32, f32) +DEF_HELPER_4(msub_s, f32, env, f32, f32, f32) #include "def-helper.h" diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index 3bf7339..ba935a8 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -784,3 +784,40 @@ void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v) env->uregs[FCR] = v & 0xfffff07f; set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status); } + +float32 HELPER(abs_s)(float32 v) +{ + return float32_abs(v); +} + +float32 HELPER(neg_s)(float32 v) +{ + return float32_chs(v); +} + +float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b) +{ + return float32_add(a, b, &env->fp_status); +} + +float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b) +{ + return float32_sub(a, b, &env->fp_status); +} + +float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b) +{ + return float32_mul(a, b, &env->fp_status); +} + +float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c) +{ + return float32_muladd(b, c, a, 0, + &env->fp_status); +} + +float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c) +{ + return float32_muladd(b, c, a, float_muladd_negate_product, + &env->fp_status); +} diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index d167e9d..a2ce286 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -1889,7 +1889,66 @@ static void disas_xtensa_insn(DisasContext *dc) case 10: /*FP0*/ HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); - TBD(); + switch (OP2) { + case 0: /*ADD.Sf*/ + gen_helper_add_s(cpu_FR[RRR_R], cpu_env, + cpu_FR[RRR_S], cpu_FR[RRR_T]); + break; + + case 1: /*SUB.Sf*/ + gen_helper_sub_s(cpu_FR[RRR_R], cpu_env, + cpu_FR[RRR_S], cpu_FR[RRR_T]); + break; + + case 2: /*MUL.Sf*/ + gen_helper_mul_s(cpu_FR[RRR_R], cpu_env, + cpu_FR[RRR_S], cpu_FR[RRR_T]); + break; + + case 4: /*MADD.Sf*/ + gen_helper_madd_s(cpu_FR[RRR_R], cpu_env, + cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]); + break; + + case 5: /*MSUB.Sf*/ + gen_helper_msub_s(cpu_FR[RRR_R], cpu_env, + cpu_FR[RRR_R], cpu_FR[RRR_S], cpu_FR[RRR_T]); + break; + + case 15: /*FP1OP*/ + switch (RRR_T) { + case 0: /*MOV.Sf*/ + tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]); + break; + + case 1: /*ABS.Sf*/ + gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]); + break; + + case 4: /*RFRf*/ + gen_window_check1(dc, RRR_R); + tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]); + break; + + case 5: /*WFRf*/ + gen_window_check1(dc, RRR_S); + tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]); + break; + + case 6: /*NEG.Sf*/ + gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]); + break; + + default: /*reserved*/ + RESERVED(); + break; + } + break; + + default: /*reserved*/ + RESERVED(); + break; + } break; case 11: /*FP1*/