From patchwork Sun Sep 9 16:04:34 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 182630 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B9F312C0086 for ; Mon, 10 Sep 2012 02:40:24 +1000 (EST) Received: from localhost ([::1]:56519 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAk1J-0004vb-S0 for incoming@patchwork.ozlabs.org; Sun, 09 Sep 2012 12:06:01 -0400 Received: from eggs.gnu.org ([208.118.235.92]:36285) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAk0d-0003X4-Py for qemu-devel@nongnu.org; Sun, 09 Sep 2012 12:05:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TAk0a-0007vj-CN for qemu-devel@nongnu.org; Sun, 09 Sep 2012 12:05:19 -0400 Received: from mail-lpp01m010-f45.google.com ([209.85.215.45]:63685) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TAk0a-0007WX-4L for qemu-devel@nongnu.org; Sun, 09 Sep 2012 12:05:16 -0400 Received: by mail-lpp01m010-f45.google.com with SMTP id z14so574040lag.4 for ; Sun, 09 Sep 2012 09:05:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=VdA+9hGJUTVlb42M3LVqTS0xVj/Euu0J/7A1EY8WfXk=; b=k5wKORMFt1/tAHCYQaqY2GRU19WfD7WLYRq/3bWz9n5v5VS4Eevq0XnBm+S/NGml/f ZHRiifyFcpf8QsfyNzRqBFc2RfA9oeMRwYMiEpmis1iDb6IB89uPZnPVAIrRlGPBeJQs uwnwAojXwJf/gIeCGxcOIAbqOACfaLHbrI8l5/eH6az7h/eQL5UZqiUyxFXgGOUlm0a2 z5+5F80fA2i0JOKj8Ccha9rNg1AH1dL++IMKq9ZrbiIa2wislEoHXH1H1fMjy0JHaUJo G8EHR/rbZnupKnroJbzHJYLBQ7WPfpqewJHDa/qTYK0CiR6x3AvwMF0jEqVgEv7EROv+ mrSw== Received: by 10.152.105.206 with SMTP id go14mr3823517lab.37.1347206715619; Sun, 09 Sep 2012 09:05:15 -0700 (PDT) Received: from octofox.metropolis ([188.134.19.124]) by mx.google.com with ESMTPS id in6sm8995530lab.1.2012.09.09.09.05.12 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 09 Sep 2012 09:05:14 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Sun, 9 Sep 2012 20:04:34 +0400 Message-Id: <1347206679-428-6-git-send-email-jcmvbkbc@gmail.com> X-Mailer: git-send-email 1.7.7.6 In-Reply-To: <1347206679-428-1-git-send-email-jcmvbkbc@gmail.com> References: <1347206679-428-1-git-send-email-jcmvbkbc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.215.45 Cc: Blue Swirl , Peter Maydell , Max Filippov Subject: [Qemu-devel] [PATCH v2 05/10] target-xtensa: add FP registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org There are 16 32-bit FP registers (f0 - f15), control and status user registers (fcr, fsr). See ISA, 4.3.10 for more details. Signed-off-by: Max Filippov --- Changes v1->v2: - add float32_val/make_float32 to fp registers accessors gdbstub.c | 8 +++++++ target-xtensa/cpu.h | 3 ++ target-xtensa/helper.h | 2 + target-xtensa/op_helper.c | 13 +++++++++++ target-xtensa/translate.c | 52 ++++++++++++++++++++++++++++++++++++++------ 5 files changed, 71 insertions(+), 7 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index 5d37dd9..c28c6b5 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -1660,6 +1660,10 @@ static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n) GET_REG32(env->uregs[reg->targno & 0xff]); break; + case 4: /*f*/ + GET_REG32(float32_val(env->fregs[reg->targno & 0x0f])); + break; + case 8: /*a*/ GET_REG32(env->regs[reg->targno & 0x0f]); break; @@ -1700,6 +1704,10 @@ static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n) env->uregs[reg->targno & 0xff] = tmp; break; + case 4: /*f*/ + env->fregs[reg->targno & 0x0f] = make_float32(tmp); + break; + case 8: /*a*/ env->regs[reg->targno & 0x0f] = tmp; break; diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 177094a..b456283 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -36,6 +36,7 @@ #include "config.h" #include "qemu-common.h" #include "cpu-defs.h" +#include "fpu/softfloat.h" #define TARGET_HAS_ICE 1 @@ -325,6 +326,8 @@ typedef struct CPUXtensaState { uint32_t sregs[256]; uint32_t uregs[256]; uint32_t phys_regs[MAX_NAREG]; + float32 fregs[16]; + float_status fp_status; xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE]; diff --git a/target-xtensa/helper.h b/target-xtensa/helper.h index 152fec0..1662552 100644 --- a/target-xtensa/helper.h +++ b/target-xtensa/helper.h @@ -36,4 +36,6 @@ DEF_HELPER_3(wsr_ibreaka, void, env, i32, i32) DEF_HELPER_3(wsr_dbreaka, void, env, i32, i32) DEF_HELPER_3(wsr_dbreakc, void, env, i32, i32) +DEF_HELPER_2(wur_fcr, void, env, i32) + #include "def-helper.h" diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index 2659c0e..3bf7339 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -771,3 +771,16 @@ void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v) } env->sregs[DBREAKC + i] = v; } + +void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v) +{ + static const int rounding_mode[] = { + float_round_nearest_even, + float_round_to_zero, + float_round_up, + float_round_down, + }; + + env->uregs[FCR] = v & 0xfffff07f; + set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status); +} diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 1900bd5..97c388a 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -70,6 +70,7 @@ typedef struct DisasContext { static TCGv_ptr cpu_env; static TCGv_i32 cpu_pc; static TCGv_i32 cpu_R[16]; +static TCGv_i32 cpu_FR[16]; static TCGv_i32 cpu_SR[256]; static TCGv_i32 cpu_UR[256]; @@ -155,6 +156,12 @@ void xtensa_translate_init(void) "ar8", "ar9", "ar10", "ar11", "ar12", "ar13", "ar14", "ar15", }; + static const char * const fregnames[] = { + "f0", "f1", "f2", "f3", + "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", + "f12", "f13", "f14", "f15", + }; int i; cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); @@ -167,6 +174,12 @@ void xtensa_translate_init(void) regnames[i]); } + for (i = 0; i < 16; i++) { + cpu_FR[i] = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUXtensaState, fregs[i]), + fregnames[i]); + } + for (i = 0; i < 256; ++i) { if (sregnames[i]) { cpu_SR[i] = tcg_global_mem_new_i32(TCG_AREG0, @@ -692,6 +705,23 @@ static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s) } } +static void gen_wur(uint32_t ur, TCGv_i32 s) +{ + switch (ur) { + case FCR: + gen_helper_wur_fcr(cpu_env, s); + break; + + case FSR: + tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80); + break; + + default: + tcg_gen_mov_i32(cpu_UR[ur], s); + break; + } +} + static void gen_load_store_alignment(DisasContext *dc, int shift, TCGv_i32 addr, bool no_hw_alignment) { @@ -1761,13 +1791,11 @@ static void disas_xtensa_insn(DisasContext *dc) case 15: /*WUR*/ gen_window_check1(dc, RRR_T); - { - if (uregnames[RSR_SR]) { - tcg_gen_mov_i32(cpu_UR[RSR_SR], cpu_R[RRR_T]); - } else { - qemu_log("WUR %d not implemented, ", RSR_SR); - TBD(); - } + if (uregnames[RSR_SR]) { + gen_wur(RSR_SR, cpu_R[RRR_T]); + } else { + qemu_log("WUR %d not implemented, ", RSR_SR); + TBD(); } break; @@ -2710,6 +2738,16 @@ void cpu_dump_state(CPUXtensaState *env, FILE *f, fprintf_function cpu_fprintf, cpu_fprintf(f, "AR%02d=%08x%c", i, env->phys_regs[i], (i % 4) == 3 ? '\n' : ' '); } + + if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) { + cpu_fprintf(f, "\n"); + + for (i = 0; i < 16; ++i) { + cpu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i, + float32_val(env->fregs[i]), + *(float *)&env->fregs[i], (i % 2) == 1 ? '\n' : ' '); + } + } } void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, int pc_pos)