From patchwork Fri Aug 3 22:40:49 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 175054 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A313F2C008E for ; Sat, 4 Aug 2012 08:41:32 +1000 (EST) Received: from localhost ([::1]:41326 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SxQYk-0007tK-Ls for incoming@patchwork.ozlabs.org; Fri, 03 Aug 2012 18:41:30 -0400 Received: from eggs.gnu.org ([208.118.235.92]:39063) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SxQYQ-0007j3-3T for qemu-devel@nongnu.org; Fri, 03 Aug 2012 18:41:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SxQYO-0003zy-R4 for qemu-devel@nongnu.org; Fri, 03 Aug 2012 18:41:09 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:58948) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SxQYO-0003zU-Kk for qemu-devel@nongnu.org; Fri, 03 Aug 2012 18:41:08 -0400 Received: by mail-pb0-f45.google.com with SMTP id ro12so1909554pbb.4 for ; Fri, 03 Aug 2012 15:41:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; bh=/2r1OWO/m4dMgVnV+4Xv8ZCaiuY9W8+9yb+SNnBbXGg=; b=cBDvFWk33Tolfpx/kmba2rpNVM+8kYrWfs3MQ5R3A797ZiHEu6kQ3gFk3rkm3lEfuJ OdnokwPcig5hQAy2jIrsi7G82KMHQ6cAQzaqKhWRvt1Y0u+BYl6ibGPQyNbNu82VhE+p 1KvKCA2O/mrmtehjJzIjQ9B5x0iZkypavgKhYnE7eDtRBc7srFtq/ftfYg2J9Na4GLuE axOWIHMcwqNg2ECHk/JMmM+qRzFVBLs6vRbaUpQjCSh5T0Soh4svZuY93FUgBHUqMACE 34+BDvW3rQGIwnYc6RS/+5WNUXBtO2jfwM8aNq8kxDamqSfd8dReK6e2F56nadf3J0yi V9DA== Received: by 10.68.218.7 with SMTP id pc7mr845830pbc.88.1344033668197; Fri, 03 Aug 2012 15:41:08 -0700 (PDT) Received: from anchor.twiddle.home ([173.160.232.49]) by mx.google.com with ESMTPS id qd2sm3721626pbb.29.2012.08.03.15.41.07 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 03 Aug 2012 15:41:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 3 Aug 2012 15:40:49 -0700 Message-Id: <1344033657-9135-3-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.7.6 In-Reply-To: <1344033657-9135-1-git-send-email-rth@twiddle.net> References: <1344033657-9135-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Subject: [Qemu-devel] [PATCH 02/10] alpha-linux-user: Work around hosted mmap allocation problems X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-alpha/cpu.h | 15 +++++++++++++-- 1 files changed, 13 insertions(+), 2 deletions(-) diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index 99f9ee1..5689760 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -40,9 +40,20 @@ #define TARGET_PAGE_BITS 13 +#ifdef CONFIG_USER_ONLY +/* ??? The kernel likes to give addresses in high memory. If the host has + more virtual address space than the guest, this can lead to impossible + allocations. Honor the long-standing assumption that only kernel addrs + are negative, but otherwise allow allocations anywhere. This could lead + to tricky emulation problems for programs doing tagged addressing, but + that's far fewer than encounter the impossible allocation problem. */ +#define TARGET_PHYS_ADDR_SPACE_BITS 63 +#define TARGET_VIRT_ADDR_SPACE_BITS 63 +#else /* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */ -#define TARGET_PHYS_ADDR_SPACE_BITS 44 -#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) +#define TARGET_PHYS_ADDR_SPACE_BITS 44 +#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) +#endif /* Alpha major type */ enum {