From patchwork Fri Apr 6 19:06:27 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 151264 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 7C2B4B700A for ; Sat, 7 Apr 2012 06:17:35 +1000 (EST) Received: from localhost ([::1]:34420 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SGEUw-0007xW-PD for incoming@patchwork.ozlabs.org; Fri, 06 Apr 2012 15:07:02 -0400 Received: from eggs.gnu.org ([208.118.235.92]:38115) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SGEUJ-0007G1-AK for qemu-devel@nongnu.org; Fri, 06 Apr 2012 15:06:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SGEUH-0007rU-Gr for qemu-devel@nongnu.org; Fri, 06 Apr 2012 15:06:22 -0400 Received: from p15195424.pureserver.info ([82.165.34.74]:56089) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SGEUD-0007qI-Ip; Fri, 06 Apr 2012 15:06:17 -0400 Received: from 93-97-95-250.zone5.bethere.co.uk ([93.97.95.250] helo=localhost.localdomain) by p15195424.pureserver.info with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.43) id 1SGEU9-0003a9-1P; Fri, 06 Apr 2012 20:06:15 +0100 From: Mark Cave-Ayland To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Date: Fri, 6 Apr 2012 20:06:27 +0100 Message-Id: <1333739187-5936-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.2.5 X-SA-Exim-Connect-IP: 93.97.95.250 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.1 (built Wed, 05 Jan 2005 10:54:05 -0500) X-SA-Exim-Scanned: Yes (on p15195424.pureserver.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) X-Received-From: 82.165.34.74 Cc: Mark Cave-Ayland Subject: [Qemu-devel] [PATCHv3] PPC: Fix interrupt MSR value for classic exception models. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Commit 41557447d30eeb944e42069513df13585f5e6c7f introduced a new method of calculating the MSR for the interrupt context. However this doesn't quite agree with the PowerISA 2.06B specification (pp. 811-814) since too many bits were being cleared. This patch corrects the calculation of the interrupt MSR for classic exception models whilst including additional comments to clarify which bits are being changed within both the MSR and the interrupt MSR. Signed-off-by: Mark Cave-Ayland Signed-off-by: Martin Sucha --- target-ppc/cpu.h | 2 ++ target-ppc/helper.c | 31 ++++++++++++++++++++++++++++--- 2 files changed, 30 insertions(+), 3 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index ca6f1cb..9a1c493 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -428,6 +428,8 @@ struct ppc_slb_t { /*****************************************************************************/ /* Machine state register bits definition */ +#define MSR_BIT(x) ((target_ulong)1 << MSR_##x) + #define MSR_SF 63 /* Sixty-four-bit mode hflags */ #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */ #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ diff --git a/target-ppc/helper.c b/target-ppc/helper.c index 63a0dec..99beace 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -2478,11 +2478,36 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp) qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx " => %08x (%02x)\n", env->nip, excp, env->error_code); - /* new srr1 value excluding must-be-zero bits */ + /* new srr1 value with interrupt-specific bits defaulting to zero */ msr = env->msr & ~0x783f0000ULL; - /* new interrupt handler msr */ - new_msr = env->msr & ((target_ulong)1 << MSR_ME); + switch (excp_model) { + case POWERPC_EXCP_STD: + case POWERPC_EXCP_601: + case POWERPC_EXCP_602: + case POWERPC_EXCP_603: + case POWERPC_EXCP_603E: + case POWERPC_EXCP_604: + case POWERPC_EXCP_7x0: + case POWERPC_EXCP_7x5: + case POWERPC_EXCP_74xx: + case POWERPC_EXCP_G2: + /* new classic interrupt handler msr (as per PowerISA 2.06B p.811 and + p.814): + 1) force the following bits to zero + IR, DR, FE0, FE1, EE, BE, FP, PMM, PR, SE + 2) default the following bits to zero (can be overidden later on) + POW, RI */ + new_msr = env->msr & ~(MSR_BIT(IR) | MSR_BIT(DR) | MSR_BIT(FE0) + | MSR_BIT(FE1) | MSR_BIT(EE) | MSR_BIT(BE) | MSR_BIT(FP) + | MSR_BIT(PMM) | MSR_BIT(PR) | MSR_BIT(SE) | MSR_BIT(POW) + | MSR_BIT(RI)); + break; + default: + /* new interrupt handler msr */ + new_msr = env->msr & ((target_ulong)1 << MSR_ME); + break; + } /* target registers */ srr0 = SPR_SRR0;