From patchwork Tue Mar 27 15:41:55 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 148978 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id C6112B6EE8 for ; Wed, 28 Mar 2012 02:42:28 +1100 (EST) Received: from localhost ([::1]:38025 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SCYXS-0000oc-Fh for incoming@patchwork.ozlabs.org; Tue, 27 Mar 2012 11:42:26 -0400 Received: from eggs.gnu.org ([208.118.235.92]:54315) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SCYX7-0000TC-NB for qemu-devel@nongnu.org; Tue, 27 Mar 2012 11:42:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SCYX2-00037R-Em for qemu-devel@nongnu.org; Tue, 27 Mar 2012 11:42:05 -0400 Received: from p15195424.pureserver.info ([82.165.34.74]:34387) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SCYWv-00031D-Jx; Tue, 27 Mar 2012 11:41:53 -0400 Received: from 93-97-95-250.zone5.bethere.co.uk ([93.97.95.250] helo=localhost.localdomain) by p15195424.pureserver.info with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.43) id 1SCYWs-0004Js-Qf; Tue, 27 Mar 2012 16:41:52 +0100 From: Mark Cave-Ayland To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Date: Tue, 27 Mar 2012 16:41:55 +0100 Message-Id: <1332862915-27501-3-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1332862915-27501-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1332862915-27501-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 93.97.95.250 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.1 (built Wed, 05 Jan 2005 10:54:05 -0500) X-SA-Exim-Scanned: Yes (on p15195424.pureserver.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) X-Received-From: 82.165.34.74 Cc: Mark Cave-Ayland Subject: [Qemu-devel] [PATCH 2/2] PPC: Fix TLB invalidation bug within the PPC interrupt handler. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Commit 41557447d30eeb944e42069513df13585f5e6c7f also introduced a subtle TLB flush bug. By applying a mask to the interrupt MSR which cleared the IR/DR bits at the start of the interrupt handler, the logic towards the end of the handler to force a TLB flush if either one of these bits were set would never be triggered. This patch simply changes the IR/DR bit check in the TLB flush logic to use the original MSR value (albeit with some interrupt-specific bits cleared) so that the IR/DR bits are preserved at the point where the check takes place. Signed-off-by: Mark Cave-Ayland Acked-by: David Gibson --- target-ppc/helper.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/target-ppc/helper.c b/target-ppc/helper.c index 653f818..84e49a1 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -2977,7 +2977,7 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp) if (asrr1 != -1) env->spr[asrr1] = env->spr[srr1]; /* If we disactivated any translation, flush TLBs */ - if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR))) + if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) tlb_flush(env, 1); if (msr_ile) {