| Message ID | 1332862915-27501-3-git-send-email-mark.cave-ayland@ilande.co.uk |
|---|---|
| State | New |
| Headers | show |
On Tue, Mar 27, 2012 at 04:41:55PM +0100, Mark Cave-Ayland wrote: > Commit 41557447d30eeb944e42069513df13585f5e6c7f also introduced a subtle TLB > flush bug. By applying a mask to the interrupt MSR which cleared the IR/DR > bits at the start of the interrupt handler, the logic towards the end of the > handler to force a TLB flush if either one of these bits were set would never > be triggered. > > This patch simply changes the IR/DR bit check in the TLB flush logic to use > the original MSR value (albeit with some interrupt-specific bits cleared) so > that the IR/DR bits are preserved at the point where the check takes place. > > Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: David Gibson <david@gibson.dropbear.id.au>
Am 28.03.2012 02:45, schrieb David Gibson: > On Tue, Mar 27, 2012 at 04:41:55PM +0100, Mark Cave-Ayland wrote: >> Commit 41557447d30eeb944e42069513df13585f5e6c7f also introduced a subtle TLB >> flush bug. By applying a mask to the interrupt MSR which cleared the IR/DR >> bits at the start of the interrupt handler, the logic towards the end of the >> handler to force a TLB flush if either one of these bits were set would never >> be triggered. >> >> This patch simply changes the IR/DR bit check in the TLB flush logic to use >> the original MSR value (albeit with some interrupt-specific bits cleared) so >> that the IR/DR bits are preserved at the point where the check takes place. >> >> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> > > Acked-by: David Gibson <david@gibson.dropbear.id.au> Thanks, compile-tested and applied to ppc-next: http://repo.or.cz/w/qemu/agraf.git/shortlog/refs/heads/ppc-next Andreas
diff --git a/target-ppc/helper.c b/target-ppc/helper.c index 653f818..84e49a1 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -2977,7 +2977,7 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp) if (asrr1 != -1) env->spr[asrr1] = env->spr[srr1]; /* If we disactivated any translation, flush TLBs */ - if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR))) + if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) tlb_flush(env, 1); if (msr_ile) {
Commit 41557447d30eeb944e42069513df13585f5e6c7f also introduced a subtle TLB flush bug. By applying a mask to the interrupt MSR which cleared the IR/DR bits at the start of the interrupt handler, the logic towards the end of the handler to force a TLB flush if either one of these bits were set would never be triggered. This patch simply changes the IR/DR bit check in the TLB flush logic to use the original MSR value (albeit with some interrupt-specific bits cleared) so that the IR/DR bits are preserved at the point where the check takes place. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> --- target-ppc/helper.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)