From patchwork Tue Mar 27 15:41:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Cave-Ayland X-Patchwork-Id: 148977 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 106A6B6EEF for ; Wed, 28 Mar 2012 02:42:17 +1100 (EST) Received: from localhost ([::1]:37483 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SCYXG-0000VH-PU for incoming@patchwork.ozlabs.org; Tue, 27 Mar 2012 11:42:14 -0400 Received: from eggs.gnu.org ([208.118.235.92]:54366) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SCYXA-0000Tm-5W for qemu-devel@nongnu.org; Tue, 27 Mar 2012 11:42:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SCYX3-00037u-Ru for qemu-devel@nongnu.org; Tue, 27 Mar 2012 11:42:07 -0400 Received: from p15195424.pureserver.info ([82.165.34.74]:34385) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SCYWu-00030Z-12; Tue, 27 Mar 2012 11:41:52 -0400 Received: from 93-97-95-250.zone5.bethere.co.uk ([93.97.95.250] helo=localhost.localdomain) by p15195424.pureserver.info with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.43) id 1SCYWq-0004Js-3C; Tue, 27 Mar 2012 16:41:50 +0100 From: Mark Cave-Ayland To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Date: Tue, 27 Mar 2012 16:41:54 +0100 Message-Id: <1332862915-27501-2-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1332862915-27501-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1332862915-27501-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 93.97.95.250 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.1 (built Wed, 05 Jan 2005 10:54:05 -0500) X-SA-Exim-Scanned: Yes (on p15195424.pureserver.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) X-Received-From: 82.165.34.74 Cc: Mark Cave-Ayland Subject: [Qemu-devel] [PATCH 1/2] PPC: Fix interrupt MSR value within the PPC interrupt handler. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Commit 41557447d30eeb944e42069513df13585f5e6c7f introduced a new method of calculating the MSR for the interrupt context. However this doesn't quite agree with the PowerISA 2.06B specification (pp. 811-814) since too many bits were being cleared. This patch corrects the calculation of the interrupt MSR whilst including additional comments to clarify which bits are being changed within both the MSR and the interrupt MSR. Signed-off-by: Mark Cave-Ayland Signed-off-by: Martin Sucha --- target-ppc/helper.c | 23 ++++++++++++++++++++--- 1 files changed, 20 insertions(+), 3 deletions(-) diff --git a/target-ppc/helper.c b/target-ppc/helper.c index 39dcc27..653f818 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -2459,6 +2459,8 @@ static inline void dump_syscall(CPUPPCState *env) /* Note that this function should be greatly optimized * when called with a constant excp, from ppc_hw_interrupt */ +#define MSR_BIT(x) ((target_ulong)1 << x) + static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp) { target_ulong msr, new_msr, vector; @@ -2478,11 +2480,26 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp) qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx " => %08x (%02x)\n", env->nip, excp, env->error_code); - /* new srr1 value excluding must-be-zero bits */ + /* new srr1 value with interrupt-specific bits defaulting to zero */ msr = env->msr & ~0x783f0000ULL; - /* new interrupt handler msr */ - new_msr = env->msr & ((target_ulong)1 << MSR_ME); + switch (excp_model) { + case POWERPC_EXCP_BOOKE: + /* new interrupt handler msr */ + new_msr = env->msr & ((target_ulong)1 << MSR_ME); + break; + + default: + /* new interrupt handler msr (as per PowerISA 2.06B p.811 and p.814): + 1) force the following bits to zero + IR, DR, FE0, FE1, EE, BE, FP, PMM, PR, SE + 2) default the following bits to zero (can be overidden later on) + RI */ + new_msr = env->msr & ~(MSR_BIT(MSR_IR) | MSR_BIT(MSR_DR) + | MSR_BIT(MSR_FE0)| MSR_BIT(MSR_FE1) | MSR_BIT(MSR_EE) + | MSR_BIT(MSR_BE) | MSR_BIT(MSR_FP) | MSR_BIT(MSR_PMM) + | MSR_BIT(MSR_PR) | MSR_BIT(MSR_SE) | MSR_BIT(MSR_RI)); + } /* target registers */ srr0 = SPR_SRR0;