From patchwork Sun Mar 25 22:27:45 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 148609 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E2AD1B6EEE for ; Mon, 26 Mar 2012 10:35:19 +1100 (EST) Received: from localhost ([::1]:60326 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SBvwC-00058I-BM for incoming@patchwork.ozlabs.org; Sun, 25 Mar 2012 18:29:24 -0400 Received: from eggs.gnu.org ([208.118.235.92]:51014) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SBvvd-0003bg-C7 for qemu-devel@nongnu.org; Sun, 25 Mar 2012 18:28:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SBvvb-0007v7-6K for qemu-devel@nongnu.org; Sun, 25 Mar 2012 18:28:48 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:61725) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SBvva-0007uY-R7 for qemu-devel@nongnu.org; Sun, 25 Mar 2012 18:28:47 -0400 Received: by pbcuo5 with SMTP id uo5so6347962pbc.4 for ; Sun, 25 Mar 2012 15:28:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=D9OG6ZS1eOwb1IplnOSCiD8ODHwjcbR02kbsgdS8wB0=; b=a9bJAo9dDXeRLWbYf4csg9HQek2cg9efxtrOp0bDSw9KxB6jcFSq3qh12dAoCFS9zF JbHQGmnQ+ld6gNeQZJLmTgrho/Sowgjq0oMOldQuJ38thvE51834BVFtWzxzO64WvIQG Er1DlfsSmMtI8WvFosrytsIc4YK7ipU9xzv06B4JMjiX3RBsWXBpAAt48XTiut/yEYDE U3B4aI9QtUJ/No6fGmCJTlHxX+7jKAMoHr9Co7d4XNA2Lsf0pDPUmdnDrCufo/GbDp/H ncDgQ2IsYc3L1A7eZJyXRCVpNuMUgRfj8oapAe4AO5vkOo1jx+QJVpQJjRk7Rm7v0UK7 zLNw== Received: by 10.68.125.134 with SMTP id mq6mr48540932pbb.74.1332714524888; Sun, 25 Mar 2012 15:28:44 -0700 (PDT) Received: from pebble.com ([173.160.232.49]) by mx.google.com with ESMTPS id l4sm11018797pbl.27.2012.03.25.15.28.43 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 25 Mar 2012 15:28:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 25 Mar 2012 15:27:45 -0700 Message-Id: <1332714477-30079-4-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.7.6 In-Reply-To: <1332714477-30079-1-git-send-email-rth@twiddle.net> References: <1332714477-30079-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Blue Swirl Subject: [Qemu-devel] [PATCH 03/15] tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Current code doesn't actually work in 32-bit mode at all. Since no one really noticed, drop the complication of v7 and v8 cpus. Eliminate the --sparc_cpu configure option and standardize macro testing on TCG_TARGET_REG_BITS. Signed-off-by: Richard Henderson --- configure | 41 ++++------------------------------------- dyngen-exec.h | 4 +--- tcg/sparc/tcg-target.c | 16 ++++------------ tcg/sparc/tcg-target.h | 7 ++++--- 4 files changed, 13 insertions(+), 55 deletions(-) diff --git a/configure b/configure index 80ca430..7741ba9 100755 --- a/configure +++ b/configure @@ -86,7 +86,6 @@ source_path=`dirname "$0"` cpu="" interp_prefix="/usr/gnemul/qemu-%M" static="no" -sparc_cpu="" cross_prefix="" audio_drv_list="" audio_card_list="ac97 es1370 sb16 hda" @@ -216,21 +215,6 @@ for opt do ;; --disable-debug-info) debug_info="no" ;; - --sparc_cpu=*) - sparc_cpu="$optarg" - case $sparc_cpu in - v7|v8|v8plus|v8plusa) - cpu="sparc" - ;; - v9) - cpu="sparc64" - ;; - *) - echo "undefined SPARC architecture. Exiting"; - exit 1 - ;; - esac - ;; esac done # OS specific @@ -284,8 +268,6 @@ elif check_define __i386__ ; then elif check_define __x86_64__ ; then cpu="x86_64" elif check_define __sparc__ ; then - # We can't check for 64 bit (when gcc is biarch) or V8PLUSA - # They must be specified using --sparc_cpu if check_define __arch64__ ; then cpu="sparc64" else @@ -749,8 +731,6 @@ for opt do ;; --enable-uname-release=*) uname_release="$optarg" ;; - --sparc_cpu=*) - ;; --enable-werror) werror="yes" ;; --disable-werror) werror="no" @@ -830,32 +810,19 @@ for opt do esac done -# -# If cpu ~= sparc and sparc_cpu hasn't been defined, plug in the right -# QEMU_CFLAGS/LDFLAGS (assume sparc_v8plus for 32-bit and sparc_v9 for 64-bit) -# host_guest_base="no" case "$cpu" in - sparc) case $sparc_cpu in - v7|v8) - QEMU_CFLAGS="-mcpu=${sparc_cpu} -D__sparc_${sparc_cpu}__ $QEMU_CFLAGS" - ;; - v8plus|v8plusa) - QEMU_CFLAGS="-mcpu=ultrasparc -D__sparc_${sparc_cpu}__ $QEMU_CFLAGS" - ;; - *) # sparc_cpu not defined in the command line - QEMU_CFLAGS="-mcpu=ultrasparc -D__sparc_v8plus__ $QEMU_CFLAGS" - esac + sparc) LDFLAGS="-m32 $LDFLAGS" - QEMU_CFLAGS="-m32 -ffixed-g2 -ffixed-g3 $QEMU_CFLAGS" + QEMU_CFLAGS="-m32 -mcpu=ultrasparc $QEMU_CFLAGS" + QEMU_CFLAGS="-ffixed-g2 -ffixed-g3 $QEMU_CFLAGS" if test "$solaris" = "no" ; then QEMU_CFLAGS="-ffixed-g1 -ffixed-g6 $QEMU_CFLAGS" - helper_cflags="-ffixed-i0" fi ;; sparc64) - QEMU_CFLAGS="-m64 -mcpu=ultrasparc -D__sparc_v9__ $QEMU_CFLAGS" LDFLAGS="-m64 $LDFLAGS" + QEMU_CFLAGS="-m64 -mcpu=ultrasparc $QEMU_CFLAGS" QEMU_CFLAGS="-ffixed-g5 -ffixed-g6 -ffixed-g7 $QEMU_CFLAGS" if test "$solaris" != "no" ; then QEMU_CFLAGS="-ffixed-g1 $QEMU_CFLAGS" diff --git a/dyngen-exec.h b/dyngen-exec.h index 083e20b..cfeef99 100644 --- a/dyngen-exec.h +++ b/dyngen-exec.h @@ -39,13 +39,11 @@ #elif defined(__sparc__) #ifdef CONFIG_SOLARIS #define AREG0 "g2" -#else -#ifdef __sparc_v9__ +#elif HOST_LONG_BITS == 64 #define AREG0 "g5" #else #define AREG0 "g6" #endif -#endif #elif defined(__s390__) #define AREG0 "r10" #elif defined(__alpha__) diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index 358a70c..257d20a 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -627,18 +627,10 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGArg ret, default: tcg_out_cmp(s, c1, c2, c2const); -#if defined(__sparc_v9__) || defined(__sparc_v8plus__) tcg_out_movi_imm13(s, ret, 0); - tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret) - | INSN_RS1(tcg_cond_to_bcond[cond]) - | MOVCC_ICC | INSN_IMM11(1)); -#else - t = gen_new_label(); - tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), t); - tcg_out_movi_imm13(s, ret, 1); - tcg_out_movi_imm13(s, ret, 0); - tcg_out_label(s, t, s->code_ptr); -#endif + tcg_out32(s, ARITH_MOVCC | INSN_RD(ret) + | INSN_RS1(tcg_cond_to_bcond[cond]) + | MOVCC_ICC | INSN_IMM11(1)); return; } @@ -768,7 +760,7 @@ static const void * const qemu_st_helpers[4] = { #endif #endif -#ifdef __arch64__ +#if TCG_TARGET_REG_BITS == 64 #define HOST_LD_OP LDX #define HOST_ST_OP STX #define HOST_SLL_OP SHIFT_SLLX diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index ee2274d..56742bf 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -67,7 +67,8 @@ typedef enum { /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_I6 -#ifdef __arch64__ + +#if TCG_TARGET_REG_BITS == 64 // Reserve space for AREG0 #define TCG_TARGET_STACK_MINFRAME (176 + 4 * (int)sizeof(long) + \ TCG_STATIC_CALL_ARGS_SIZE) @@ -81,7 +82,7 @@ typedef enum { #define TCG_TARGET_STACK_ALIGN 8 #endif -#ifdef __arch64__ +#if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_EXTEND_ARGS 1 #endif @@ -128,7 +129,7 @@ typedef enum { /* Note: must be synced with dyngen-exec.h */ #ifdef CONFIG_SOLARIS #define TCG_AREG0 TCG_REG_G2 -#elif defined(__sparc_v9__) +#elif HOST_LONG_BITS == 64 #define TCG_AREG0 TCG_REG_G5 #else #define TCG_AREG0 TCG_REG_G6