From patchwork Tue Jan 17 14:27:26 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 136480 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D1FF9B6EEA for ; Wed, 18 Jan 2012 01:27:49 +1100 (EST) Received: from localhost ([::1]:58269 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RnA0p-00055c-QA for incoming@patchwork.ozlabs.org; Tue, 17 Jan 2012 09:27:47 -0500 Received: from eggs.gnu.org ([140.186.70.92]:38710) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RnA0f-00054o-8E for qemu-devel@nongnu.org; Tue, 17 Jan 2012 09:27:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RnA0X-0004yZ-OI for qemu-devel@nongnu.org; Tue, 17 Jan 2012 09:27:37 -0500 Received: from mnementh.archaic.org.uk ([81.2.115.146]:52205) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RnA0X-0004y9-Gx for qemu-devel@nongnu.org; Tue, 17 Jan 2012 09:27:29 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1RnA0U-0005hr-Mq; Tue, 17 Jan 2012 14:27:26 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 17 Jan 2012 14:27:26 +0000 Message-Id: <1326810446-21912-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 81.2.115.146 Cc: Alexander Graf , patches@linaro.org Subject: [Qemu-devel] [PATCH] target-arm: Fix implementation of TLB invalidate operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Fix some bugs in the implementation of the TLB invalidate operations on ARM: * the 'invalidate all' op was not passing flush_global=1 to tlb_flush(); this doesn't have a practical effect since tlb_flush() currently ignores that argument, but is semantically incorrect * 'invalidate by address for all ASIDs' was implemented as flushing the whole TLB, which invalidates much more than strictly necessary. Use tlb_flush_page() instead. We also annotate the ops with the ARM ARM official acronyms. Signed-off-by: Peter Maydell --- target-arm/helper.c | 13 ++++++------- 1 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 00458fc..f11279e 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1610,18 +1610,17 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val) break; case 8: /* MMU TLB control. */ switch (op2) { - case 0: /* Invalidate all. */ - tlb_flush(env, 0); + case 0: /* Invalidate all (TLBIALL) */ + tlb_flush(env, 1); break; - case 1: /* Invalidate single TLB entry. */ + case 1: /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ tlb_flush_page(env, val & TARGET_PAGE_MASK); break; - case 2: /* Invalidate on ASID. */ + case 2: /* Invalidate by ASID (TLBIASID) */ tlb_flush(env, val == 0); break; - case 3: /* Invalidate single entry on MVA. */ - /* ??? This is like case 1, but ignores ASID. */ - tlb_flush(env, 1); + case 3: /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ + tlb_flush_page(env, val & TARGET_PAGE_MASK); break; default: goto bad_reg;