From patchwork Sat Jan 7 20:09:37 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 134871 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 696CFB6F7E for ; Sun, 8 Jan 2012 07:40:21 +1100 (EST) Received: from localhost ([::1]:36130 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rjcax-0005PP-1U for incoming@patchwork.ozlabs.org; Sat, 07 Jan 2012 15:10:27 -0500 Received: from eggs.gnu.org ([140.186.70.92]:39612) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RjcaP-0004Jc-Jg for qemu-devel@nongnu.org; Sat, 07 Jan 2012 15:09:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RjcaM-0001f0-Oy for qemu-devel@nongnu.org; Sat, 07 Jan 2012 15:09:53 -0500 Received: from hall.aurel32.net ([88.191.126.93]:43922) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RjcaM-0001ep-Ib; Sat, 07 Jan 2012 15:09:50 -0500 Received: from [2001:470:d4ed:0:5e26:aff:fe2b:6f5b] (helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1RjcaL-0004CJ-RL; Sat, 07 Jan 2012 21:09:49 +0100 Received: from aurel32 by volta.aurel32.net with local (Exim 4.77) (envelope-from ) id 1RjcaK-0000Kv-Av; Sat, 07 Jan 2012 21:09:48 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sat, 7 Jan 2012 21:09:37 +0100 Message-Id: <1325966978-940-4-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1325966978-940-1-git-send-email-aurelien@aurel32.net> References: <1325966978-940-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 88.191.126.93 Cc: qemu-stable@nongnu.org, Aurelien Jarno Subject: [Qemu-devel] [PATCH 3/4] target-i386: fix dpps and dppd SSE2 instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The helpers implemented dpps and dppd SSE instructions are not passing the correct argument types to the softfloat functions. While they do work anyway providing a correct behaviour, this patch fixes that. Signed-off-by: Aurelien Jarno --- target-i386/ops_sse.h | 28 ++++++++++++++-------------- 1 files changed, 14 insertions(+), 14 deletions(-) diff --git a/target-i386/ops_sse.h b/target-i386/ops_sse.h index a185bfb..adfe822 100644 --- a/target-i386/ops_sse.h +++ b/target-i386/ops_sse.h @@ -1770,44 +1770,44 @@ SSE_HELPER_I(helper_pblendw, W, 8, FBLENDP) void glue(helper_dpps, SUFFIX) (Reg *d, Reg *s, uint32_t mask) { - float32 iresult = 0 /*float32_zero*/; + float32 iresult = float32_zero; if (mask & (1 << 4)) iresult = float32_add(iresult, - float32_mul(d->L(0), s->L(0), &env->sse_status), + float32_mul(d->XMM_S(0), s->XMM_S(0), &env->sse_status), &env->sse_status); if (mask & (1 << 5)) iresult = float32_add(iresult, - float32_mul(d->L(1), s->L(1), &env->sse_status), + float32_mul(d->XMM_S(1), s->XMM_S(1), &env->sse_status), &env->sse_status); if (mask & (1 << 6)) iresult = float32_add(iresult, - float32_mul(d->L(2), s->L(2), &env->sse_status), + float32_mul(d->XMM_S(2), s->XMM_S(2), &env->sse_status), &env->sse_status); if (mask & (1 << 7)) iresult = float32_add(iresult, - float32_mul(d->L(3), s->L(3), &env->sse_status), + float32_mul(d->XMM_S(3), s->XMM_S(3), &env->sse_status), &env->sse_status); - d->L(0) = (mask & (1 << 0)) ? iresult : 0 /*float32_zero*/; - d->L(1) = (mask & (1 << 1)) ? iresult : 0 /*float32_zero*/; - d->L(2) = (mask & (1 << 2)) ? iresult : 0 /*float32_zero*/; - d->L(3) = (mask & (1 << 3)) ? iresult : 0 /*float32_zero*/; + d->XMM_S(0) = (mask & (1 << 0)) ? iresult : float32_zero; + d->XMM_S(1) = (mask & (1 << 1)) ? iresult : float32_zero; + d->XMM_S(2) = (mask & (1 << 2)) ? iresult : float32_zero; + d->XMM_S(3) = (mask & (1 << 3)) ? iresult : float32_zero; } void glue(helper_dppd, SUFFIX) (Reg *d, Reg *s, uint32_t mask) { - float64 iresult = 0 /*float64_zero*/; + float64 iresult = float64_zero; if (mask & (1 << 4)) iresult = float64_add(iresult, - float64_mul(d->Q(0), s->Q(0), &env->sse_status), + float64_mul(d->XMM_D(0), s->XMM_D(0), &env->sse_status), &env->sse_status); if (mask & (1 << 5)) iresult = float64_add(iresult, - float64_mul(d->Q(1), s->Q(1), &env->sse_status), + float64_mul(d->XMM_D(1), s->XMM_D(1), &env->sse_status), &env->sse_status); - d->Q(0) = (mask & (1 << 0)) ? iresult : 0 /*float64_zero*/; - d->Q(1) = (mask & (1 << 1)) ? iresult : 0 /*float64_zero*/; + d->XMM_D(0) = (mask & (1 << 0)) ? iresult : float64_zero; + d->XMM_D(1) = (mask & (1 << 1)) ? iresult : float64_zero; } void glue(helper_mpsadbw, SUFFIX) (Reg *d, Reg *s, uint32_t offset)