From patchwork Sat Jan 7 20:09:35 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 134862 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D571CB6F7E for ; Sun, 8 Jan 2012 07:10:22 +1100 (EST) Received: from localhost ([::1]:34358 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rjcak-0004RD-Ph for incoming@patchwork.ozlabs.org; Sat, 07 Jan 2012 15:10:14 -0500 Received: from eggs.gnu.org ([140.186.70.92]:39578) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RjcaN-0004Az-6Q for qemu-devel@nongnu.org; Sat, 07 Jan 2012 15:09:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RjcaM-0001eb-24 for qemu-devel@nongnu.org; Sat, 07 Jan 2012 15:09:51 -0500 Received: from hall.aurel32.net ([88.191.126.93]:43919) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RjcaL-0001eR-Nk; Sat, 07 Jan 2012 15:09:49 -0500 Received: from [2001:470:d4ed:0:5e26:aff:fe2b:6f5b] (helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1RjcaL-0004CH-0O; Sat, 07 Jan 2012 21:09:49 +0100 Received: from aurel32 by volta.aurel32.net with local (Exim 4.77) (envelope-from ) id 1RjcaJ-0000Kq-SK; Sat, 07 Jan 2012 21:09:47 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sat, 7 Jan 2012 21:09:35 +0100 Message-Id: <1325966978-940-2-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1325966978-940-1-git-send-email-aurelien@aurel32.net> References: <1325966978-940-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 88.191.126.93 Cc: qemu-stable@nongnu.org, Aurelien Jarno Subject: [Qemu-devel] [PATCH 1/4] target-i386: fix {min, max}{pd, ps, sd, ss} SSE2 instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org minpd, minps, minsd, minss and maxpd, maxps, maxsd, maxss SSE2 instructions have been broken when switching target-i386 to softfloat. It's not possible to use comparison instructions on float types anymore to softfloat, so use the floatXX_min anf floatXX_max functions instead. As a bonus it implements the correct NaNs behaviour, so let's remove this from the TODO. It fixes GDM screen display on Debian Lenny. Signed-off-by: Aurelien Jarno --- target-i386/TODO | 1 - target-i386/ops_sse.h | 4 ++-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/target-i386/TODO b/target-i386/TODO index c8ada07..a8d69cf 100644 --- a/target-i386/TODO +++ b/target-i386/TODO @@ -15,7 +15,6 @@ Correctness issues: - DRx register support - CR0.AC emulation - SSE alignment checks -- fix SSE min/max with nans Optimizations/Features: diff --git a/target-i386/ops_sse.h b/target-i386/ops_sse.h index 47dde78..a743c85 100644 --- a/target-i386/ops_sse.h +++ b/target-i386/ops_sse.h @@ -584,8 +584,8 @@ void helper_ ## name ## sd (Reg *d, Reg *s)\ #define FPU_SUB(size, a, b) float ## size ## _sub(a, b, &env->sse_status) #define FPU_MUL(size, a, b) float ## size ## _mul(a, b, &env->sse_status) #define FPU_DIV(size, a, b) float ## size ## _div(a, b, &env->sse_status) -#define FPU_MIN(size, a, b) (a) < (b) ? (a) : (b) -#define FPU_MAX(size, a, b) (a) > (b) ? (a) : (b) +#define FPU_MIN(size, a, b) float ## size ## _min(a, b, &env->sse_status) +#define FPU_MAX(size, a, b) float ## size ## _max(a, b, &env->sse_status) #define FPU_SQRT(size, a, b) float ## size ## _sqrt(b, &env->sse_status) SSE_HELPER_S(add, FPU_ADD)