From patchwork Sat Dec 31 04:54:50 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 133728 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 5C504B6FC4 for ; Sat, 31 Dec 2011 15:57:14 +1100 (EST) Received: from localhost ([::1]:58754 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rgr0I-0002Bv-9U for incoming@patchwork.ozlabs.org; Fri, 30 Dec 2011 23:57:10 -0500 Received: from eggs.gnu.org ([140.186.70.92]:52050) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RgqzU-0008Tc-Rg for qemu-devel@nongnu.org; Fri, 30 Dec 2011 23:56:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RgqzT-0000fb-H5 for qemu-devel@nongnu.org; Fri, 30 Dec 2011 23:56:20 -0500 Received: from mail-gx0-f173.google.com ([209.85.161.173]:45215) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RgqzT-0000f5-Cr for qemu-devel@nongnu.org; Fri, 30 Dec 2011 23:56:19 -0500 Received: by mail-gx0-f173.google.com with SMTP id k1so10741955ggn.4 for ; Fri, 30 Dec 2011 20:56:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=daq7YnelfWwil/Idoj5JwIPmwddVjsZ2DloCsG5ByHY=; b=CNr/9m/huAfRSwKbuWVsn8bgAJmnIqRwIucCFAo3UoDoAUqIifL0FIljJ3vHI27W3F bfF1FHj4S0WxK3zVvlv4G4K1VRMrya7Ta41BQboPeWsDxyD+lyO2evvBuOQUoNaXRs3O niHg6RgCcyttTAP8QOOzf7hvnDdErYj6gu8wA= Received: by 10.101.158.17 with SMTP id k17mr5707251ano.67.1325307379037; Fri, 30 Dec 2011 20:56:19 -0800 (PST) Received: from pebble.com ([101.172.149.215]) by mx.google.com with ESMTPS id v8sm11097049yhi.10.2011.12.30.20.56.16 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 30 Dec 2011 20:56:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 31 Dec 2011 15:54:50 +1100 Message-Id: <1325307291-6334-3-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1325307291-6334-1-git-send-email-rth@twiddle.net> References: <1325307291-6334-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.161.173 Cc: peter.maydell@linaro.org, afaerber@suse.de, Aurelien Jarno Subject: [Qemu-devel] [PATCH 3/4] target-mips: Add accessors for the two 32-bit halves of a 64-bit FPR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Not much used yet, but more users to come. Signed-off-by: Richard Henderson --- target-mips/translate.c | 46 ++++++++++++++++++++++++++++++---------------- 1 files changed, 30 insertions(+), 16 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index b6a7aeb..8908c8c 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -751,6 +751,29 @@ static void gen_store_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg) } } +static void gen_load_fpr_pair(DisasContext *ctx, TCGv_i32 tl, + TCGv_i32 th, int reg) +{ + gen_load_fpr32 (ctx, tl, reg); + gen_load_fpr32h (ctx, th, reg); +} + +static void gen_store_fpr_pair(DisasContext *ctx, TCGv_i32 tl, + TCGv_i32 th, int reg) +{ +#if TCG_TARGET_REG_BITS == 32 + tcg_gen_mov_i32(TCGV_LOW(fpu_f64[reg]), tl); + tcg_gen_mov_i32(TCGV_HIGH(fpu_f64[reg]), th); +#else + if (ctx->hflags & MIPS_HFLAG_F64) { + tcg_gen_concat32_i64(fpu_f64[reg], tl, th); + } else { + tcg_gen_mov_i32(fpu_f32[reg], tl); + tcg_gen_mov_i32(fpu_fh32[reg], th); + } +#endif +} + static inline int get_fp_bit (int cc) { if (cc) @@ -7687,8 +7710,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); - gen_store_fpr32h(ctx, fp0, fd); - gen_store_fpr32(ctx, fp1, fd); + gen_store_fpr_pair(ctx, fp1, fp0, fd); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); } @@ -7702,8 +7724,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32h(ctx, fp1, ft); - gen_store_fpr32(ctx, fp1, fd); - gen_store_fpr32h(ctx, fp0, fd); + gen_store_fpr_pair(ctx, fp1, fp0, fd); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); } @@ -7717,8 +7738,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr32h(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); - gen_store_fpr32(ctx, fp1, fd); - gen_store_fpr32h(ctx, fp0, fd); + gen_store_fpr_pair(ctx, fp1, fp0, fd); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); } @@ -7732,8 +7752,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr32h(ctx, fp0, fs); gen_load_fpr32h(ctx, fp1, ft); - gen_store_fpr32(ctx, fp1, fd); - gen_store_fpr32h(ctx, fp0, fd); + gen_store_fpr_pair(ctx, fp1, fp0, fd); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); } @@ -7905,10 +7924,8 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, tcg_gen_andi_tl(t0, t0, 0x7); tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1); - gen_load_fpr32(ctx, fp, fs); - gen_load_fpr32h(ctx, fph, fs); - gen_store_fpr32(ctx, fp, fd); - gen_store_fpr32h(ctx, fph, fd); + gen_load_fpr_pair(ctx, fp, fph, fs); + gen_store_fpr_pair(ctx, fp, fph, fd); tcg_gen_br(l2); gen_set_label(l1); tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2); @@ -7916,14 +7933,11 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, #ifdef TARGET_WORDS_BIGENDIAN gen_load_fpr32(ctx, fp, fs); gen_load_fpr32h(ctx, fph, ft); - gen_store_fpr32h(ctx, fp, fd); - gen_store_fpr32(ctx, fph, fd); #else gen_load_fpr32h(ctx, fph, fs); gen_load_fpr32(ctx, fp, ft); - gen_store_fpr32(ctx, fph, fd); - gen_store_fpr32h(ctx, fp, fd); #endif + gen_store_fpr_pair(ctx, fph, fp, fd); gen_set_label(l2); tcg_temp_free_i32(fp); tcg_temp_free_i32(fph);