From patchwork Sat Dec 31 04:54:48 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 133726 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 10BBBB6FC9 for ; Sat, 31 Dec 2011 15:56:43 +1100 (EST) Received: from localhost ([::1]:55253 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rgqzo-0000Kq-0y for incoming@patchwork.ozlabs.org; Fri, 30 Dec 2011 23:56:40 -0500 Received: from eggs.gnu.org ([140.186.70.92]:52043) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RgqzS-0008S7-Ul for qemu-devel@nongnu.org; Fri, 30 Dec 2011 23:56:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RgqzO-0000f9-PG for qemu-devel@nongnu.org; Fri, 30 Dec 2011 23:56:18 -0500 Received: from mail-gx0-f173.google.com ([209.85.161.173]:45215) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RgqzO-0000f5-GN for qemu-devel@nongnu.org; Fri, 30 Dec 2011 23:56:14 -0500 Received: by ggnk1 with SMTP id k1so10741955ggn.4 for ; Fri, 30 Dec 2011 20:56:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer; bh=sAL7Roiv8UhaROoiucdNq7ysVrWE95yRQZWmT2GKHRE=; b=uae+rqY/LJLkAPVrByQ5EmCmkhFDQhxhTOktTrTYmBCjd5qngtrap7XRU/Q44eJ3t1 HlbVP+e7xQ+EGR7nNpqgxwelWBbjJJC5hjNTbjC+2Y3u0XkRXdxKXVuHUkB3ceuQ/l0Z l09WGxq/g+7n5qrHZxaZOdr7lu6GMt98dYitw= Received: by 10.236.93.4 with SMTP id k4mr53813667yhf.114.1325307372746; Fri, 30 Dec 2011 20:56:12 -0800 (PST) Received: from pebble.com ([101.172.149.215]) by mx.google.com with ESMTPS id v8sm11097049yhi.10.2011.12.30.20.56.08 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 30 Dec 2011 20:56:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 31 Dec 2011 15:54:48 +1100 Message-Id: <1325307291-6334-1-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.7.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.161.173 Cc: peter.maydell@linaro.org, afaerber@suse.de, Aurelien Jarno Subject: [Qemu-devel] [PATCH 1/4] target-mips: Pass DisasContext to fpr32 load/store routines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The large mechanical change in support of a follow-on patch that changes the representation of the fp registers. Signed-off-by: Richard Henderson --- target-mips/translate.c | 308 +++++++++++++++++++++++------------------------ 1 files changed, 151 insertions(+), 157 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index d5b1c76..d2aeff0 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -647,22 +647,22 @@ static inline void gen_store_srsgpr (int from, int to) } /* Floating point register moves. */ -static inline void gen_load_fpr32 (TCGv_i32 t, int reg) +static inline void gen_load_fpr32 (DisasContext *ctx, TCGv_i32 t, int reg) { tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX])); } -static inline void gen_store_fpr32 (TCGv_i32 t, int reg) +static inline void gen_store_fpr32 (DisasContext *ctx, TCGv_i32 t, int reg) { tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[FP_ENDIAN_IDX])); } -static inline void gen_load_fpr32h (TCGv_i32 t, int reg) +static inline void gen_load_fpr32h (DisasContext *ctx, TCGv_i32 t, int reg) { tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX])); } -static inline void gen_store_fpr32h (TCGv_i32 t, int reg) +static inline void gen_store_fpr32h (DisasContext *ctx, TCGv_i32 t, int reg) { tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, active_fpu.fpr[reg].w[!FP_ENDIAN_IDX])); } @@ -674,8 +674,8 @@ static inline void gen_load_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg) } else { TCGv_i32 t0 = tcg_temp_new_i32(); TCGv_i32 t1 = tcg_temp_new_i32(); - gen_load_fpr32(t0, reg & ~1); - gen_load_fpr32(t1, reg | 1); + gen_load_fpr32(ctx, t0, reg & ~1); + gen_load_fpr32(ctx, t1, reg | 1); tcg_gen_concat_i32_i64(t, t0, t1); tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); @@ -690,10 +690,10 @@ static inline void gen_store_fpr64 (DisasContext *ctx, TCGv_i64 t, int reg) TCGv_i64 t0 = tcg_temp_new_i64(); TCGv_i32 t1 = tcg_temp_new_i32(); tcg_gen_trunc_i64_i32(t1, t); - gen_store_fpr32(t1, reg & ~1); + gen_store_fpr32(ctx, t1, reg & ~1); tcg_gen_shri_i64(t0, t, 32); tcg_gen_trunc_i64_i32(t1, t0); - gen_store_fpr32(t1, reg | 1); + gen_store_fpr32(ctx, t1, reg | 1); tcg_temp_free_i32(t1); tcg_temp_free_i64(t0); } @@ -847,12 +847,6 @@ static inline void check_mips_64(DisasContext *ctx) generate_exception(ctx, EXCP_RI); } -/* Define small wrappers for gen_load_fpr* so that we have a uniform - calling interface for 32 and 64-bit FPRs. No sense in changing - all callers for gen_load_fpr32 when we need the CTX parameter for - this one use. */ -#define gen_ldcmp_fpr32(ctx, x, y) gen_load_fpr32(x, y) -#define gen_ldcmp_fpr64(ctx, x, y) gen_load_fpr64(ctx, x, y) #define FOP_CONDS(type, abs, fmt, ifmt, bits) \ static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \ int ft, int fs, int cc) \ @@ -875,8 +869,8 @@ static inline void gen_cmp ## type ## _ ## fmt(DisasContext *ctx, int n, \ } \ break; \ } \ - gen_ldcmp_fpr##bits (ctx, fp0, fs); \ - gen_ldcmp_fpr##bits (ctx, fp1, ft); \ + gen_load_fpr##bits (ctx, fp0, fs); \ + gen_load_fpr##bits (ctx, fp1, ft); \ switch (n) { \ case 0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, fp0, fp1, cc); break;\ case 1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, fp0, fp1, cc); break;\ @@ -1271,7 +1265,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx); tcg_gen_trunc_tl_i32(fp0, t0); - gen_store_fpr32(fp0, ft); + gen_store_fpr32(ctx, fp0, ft); tcg_temp_free_i32(fp0); } opn = "lwc1"; @@ -1281,7 +1275,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv t1 = tcg_temp_new(); - gen_load_fpr32(fp0, ft); + gen_load_fpr32(ctx, fp0, ft); tcg_gen_extu_i32_tl(t1, fp0); tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); tcg_temp_free(t1); @@ -5706,13 +5700,13 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd, if (h == 0) { TCGv_i32 fp0 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, rt); + gen_load_fpr32(ctx, fp0, rt); tcg_gen_ext_i32_tl(t0, fp0); tcg_temp_free_i32(fp0); } else { TCGv_i32 fp0 = tcg_temp_new_i32(); - gen_load_fpr32h(fp0, rt); + gen_load_fpr32h(ctx, fp0, rt); tcg_gen_ext_i32_tl(t0, fp0); tcg_temp_free_i32(fp0); } @@ -5905,13 +5899,13 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt, TCGv_i32 fp0 = tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(fp0, t0); - gen_store_fpr32(fp0, rd); + gen_store_fpr32(ctx, fp0, rd); tcg_temp_free_i32(fp0); } else { TCGv_i32 fp0 = tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(fp0, t0); - gen_store_fpr32h(fp0, rd); + gen_store_fpr32h(ctx, fp0, rd); tcg_temp_free_i32(fp0); } break; @@ -6327,7 +6321,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) { TCGv_i32 fp0 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); + gen_load_fpr32(ctx, fp0, fs); tcg_gen_ext_i32_tl(t0, fp0); tcg_temp_free_i32(fp0); } @@ -6340,7 +6334,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) TCGv_i32 fp0 = tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(fp0, t0); - gen_store_fpr32(fp0, fs); + gen_store_fpr32(ctx, fp0, fs); tcg_temp_free_i32(fp0); } opn = "mtc1"; @@ -6371,7 +6365,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) { TCGv_i32 fp0 = tcg_temp_new_i32(); - gen_load_fpr32h(fp0, fs); + gen_load_fpr32h(ctx, fp0, fs); tcg_gen_ext_i32_tl(t0, fp0); tcg_temp_free_i32(fp0); } @@ -6384,7 +6378,7 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) TCGv_i32 fp0 = tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(fp0, t0); - gen_store_fpr32h(fp0, fs); + gen_store_fpr32h(ctx, fp0, fs); tcg_temp_free_i32(fp0); } opn = "mthc1"; @@ -6430,7 +6424,7 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf) gen_set_label(l1); } -static inline void gen_movcf_s (int fs, int fd, int cc, int tf) +static void gen_movcf_s (DisasContext *ctx, int fs, int fd, int cc, int tf) { int cond; TCGv_i32 t0 = tcg_temp_new_i32(); @@ -6443,13 +6437,13 @@ static inline void gen_movcf_s (int fs, int fd, int cc, int tf) tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); - gen_load_fpr32(t0, fs); - gen_store_fpr32(t0, fd); + gen_load_fpr32(ctx, t0, fs); + gen_store_fpr32(ctx, t0, fd); gen_set_label(l1); tcg_temp_free_i32(t0); } -static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int tf) +static void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int tf) { int cond; TCGv_i32 t0 = tcg_temp_new_i32(); @@ -6471,7 +6465,7 @@ static inline void gen_movcf_d (DisasContext *ctx, int fs, int fd, int cc, int t gen_set_label(l1); } -static inline void gen_movcf_ps (int fs, int fd, int cc, int tf) +static void gen_movcf_ps (DisasContext *ctx, int fs, int fd, int cc, int tf) { int cond; TCGv_i32 t0 = tcg_temp_new_i32(); @@ -6485,14 +6479,14 @@ static inline void gen_movcf_ps (int fs, int fd, int cc, int tf) tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); - gen_load_fpr32(t0, fs); - gen_store_fpr32(t0, fd); + gen_load_fpr32(ctx, t0, fs); + gen_store_fpr32(ctx, t0, fd); gen_set_label(l1); tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc+1)); tcg_gen_brcondi_i32(cond, t0, 0, l2); - gen_load_fpr32h(t0, fs); - gen_store_fpr32h(t0, fd); + gen_load_fpr32h(ctx, t0, fs); + gen_store_fpr32h(ctx, t0, fd); tcg_temp_free_i32(t0); gen_set_label(l2); } @@ -6547,11 +6541,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); - gen_load_fpr32(fp1, ft); + gen_load_fpr32(ctx, fp0, fs); + gen_load_fpr32(ctx, fp1, ft); gen_helper_float_add_s(fp0, fp0, fp1); tcg_temp_free_i32(fp1); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "add.s"; @@ -6562,11 +6556,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); - gen_load_fpr32(fp1, ft); + gen_load_fpr32(ctx, fp0, fs); + gen_load_fpr32(ctx, fp1, ft); gen_helper_float_sub_s(fp0, fp0, fp1); tcg_temp_free_i32(fp1); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "sub.s"; @@ -6577,11 +6571,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); - gen_load_fpr32(fp1, ft); + gen_load_fpr32(ctx, fp0, fs); + gen_load_fpr32(ctx, fp1, ft); gen_helper_float_mul_s(fp0, fp0, fp1); tcg_temp_free_i32(fp1); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "mul.s"; @@ -6592,11 +6586,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); - gen_load_fpr32(fp1, ft); + gen_load_fpr32(ctx, fp0, fs); + gen_load_fpr32(ctx, fp1, ft); gen_helper_float_div_s(fp0, fp0, fp1); tcg_temp_free_i32(fp1); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "div.s"; @@ -6606,9 +6600,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, { TCGv_i32 fp0 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); + gen_load_fpr32(ctx, fp0, fs); gen_helper_float_sqrt_s(fp0, fp0); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "sqrt.s"; @@ -6617,9 +6611,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, { TCGv_i32 fp0 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); + gen_load_fpr32(ctx, fp0, fs); gen_helper_float_abs_s(fp0, fp0); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "abs.s"; @@ -6628,8 +6622,8 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, { TCGv_i32 fp0 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); - gen_store_fpr32(fp0, fd); + gen_load_fpr32(ctx, fp0, fs); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "mov.s"; @@ -6638,9 +6632,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, { TCGv_i32 fp0 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); + gen_load_fpr32(ctx, fp0, fs); gen_helper_float_chs_s(fp0, fp0); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "neg.s"; @@ -6651,7 +6645,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp32 = tcg_temp_new_i32(); TCGv_i64 fp64 = tcg_temp_new_i64(); - gen_load_fpr32(fp32, fs); + gen_load_fpr32(ctx, fp32, fs); gen_helper_float_roundl_s(fp64, fp32); tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); @@ -6665,7 +6659,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp32 = tcg_temp_new_i32(); TCGv_i64 fp64 = tcg_temp_new_i64(); - gen_load_fpr32(fp32, fs); + gen_load_fpr32(ctx, fp32, fs); gen_helper_float_truncl_s(fp64, fp32); tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); @@ -6679,7 +6673,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp32 = tcg_temp_new_i32(); TCGv_i64 fp64 = tcg_temp_new_i64(); - gen_load_fpr32(fp32, fs); + gen_load_fpr32(ctx, fp32, fs); gen_helper_float_ceill_s(fp64, fp32); tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); @@ -6693,7 +6687,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp32 = tcg_temp_new_i32(); TCGv_i64 fp64 = tcg_temp_new_i64(); - gen_load_fpr32(fp32, fs); + gen_load_fpr32(ctx, fp32, fs); gen_helper_float_floorl_s(fp64, fp32); tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); @@ -6705,9 +6699,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, { TCGv_i32 fp0 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); + gen_load_fpr32(ctx, fp0, fs); gen_helper_float_roundw_s(fp0, fp0); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "round.w.s"; @@ -6716,9 +6710,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, { TCGv_i32 fp0 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); + gen_load_fpr32(ctx, fp0, fs); gen_helper_float_truncw_s(fp0, fp0); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "trunc.w.s"; @@ -6727,9 +6721,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, { TCGv_i32 fp0 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); + gen_load_fpr32(ctx, fp0, fs); gen_helper_float_ceilw_s(fp0, fp0); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "ceil.w.s"; @@ -6738,15 +6732,15 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, { TCGv_i32 fp0 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); + gen_load_fpr32(ctx, fp0, fs); gen_helper_float_floorw_s(fp0, fp0); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "floor.w.s"; break; case OPC_MOVCF_S: - gen_movcf_s(fs, fd, (ft >> 2) & 0x7, ft & 0x1); + gen_movcf_s(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); opn = "movcf.s"; break; case OPC_MOVZ_S: @@ -6758,8 +6752,8 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[ft], 0, l1); } fp0 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); - gen_store_fpr32(fp0, fd); + gen_load_fpr32(ctx, fp0, fs); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); gen_set_label(l1); } @@ -6773,8 +6767,8 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, if (ft != 0) { tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[ft], 0, l1); fp0 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); - gen_store_fpr32(fp0, fd); + gen_load_fpr32(ctx, fp0, fs); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); gen_set_label(l1); } @@ -6786,9 +6780,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, { TCGv_i32 fp0 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); + gen_load_fpr32(ctx, fp0, fs); gen_helper_float_recip_s(fp0, fp0); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "recip.s"; @@ -6798,9 +6792,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, { TCGv_i32 fp0 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); + gen_load_fpr32(ctx, fp0, fs); gen_helper_float_rsqrt_s(fp0, fp0); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "rsqrt.s"; @@ -6811,11 +6805,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); - gen_load_fpr32(fp1, fd); + gen_load_fpr32(ctx, fp0, fs); + gen_load_fpr32(ctx, fp1, fd); gen_helper_float_recip2_s(fp0, fp0, fp1); tcg_temp_free_i32(fp1); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "recip2.s"; @@ -6825,9 +6819,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, { TCGv_i32 fp0 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); + gen_load_fpr32(ctx, fp0, fs); gen_helper_float_recip1_s(fp0, fp0); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "recip1.s"; @@ -6837,9 +6831,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, { TCGv_i32 fp0 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); + gen_load_fpr32(ctx, fp0, fs); gen_helper_float_rsqrt1_s(fp0, fp0); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "rsqrt1.s"; @@ -6850,11 +6844,11 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); - gen_load_fpr32(fp1, ft); + gen_load_fpr32(ctx, fp0, fs); + gen_load_fpr32(ctx, fp1, ft); gen_helper_float_rsqrt2_s(fp0, fp0, fp1); tcg_temp_free_i32(fp1); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "rsqrt2.s"; @@ -6865,7 +6859,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp32 = tcg_temp_new_i32(); TCGv_i64 fp64 = tcg_temp_new_i64(); - gen_load_fpr32(fp32, fs); + gen_load_fpr32(ctx, fp32, fs); gen_helper_float_cvtd_s(fp64, fp32); tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); @@ -6877,9 +6871,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, { TCGv_i32 fp0 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); + gen_load_fpr32(ctx, fp0, fs); gen_helper_float_cvtw_s(fp0, fp0); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "cvt.w.s"; @@ -6890,7 +6884,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp32 = tcg_temp_new_i32(); TCGv_i64 fp64 = tcg_temp_new_i64(); - gen_load_fpr32(fp32, fs); + gen_load_fpr32(ctx, fp32, fs); gen_helper_float_cvtl_s(fp64, fp32); tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); @@ -6905,8 +6899,8 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp32_0 = tcg_temp_new_i32(); TCGv_i32 fp32_1 = tcg_temp_new_i32(); - gen_load_fpr32(fp32_0, fs); - gen_load_fpr32(fp32_1, ft); + gen_load_fpr32(ctx, fp32_0, fs); + gen_load_fpr32(ctx, fp32_1, ft); tcg_gen_concat_i32_i64(fp64, fp32_0, fp32_1); tcg_temp_free_i32(fp32_1); tcg_temp_free_i32(fp32_0); @@ -7107,7 +7101,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp64, fs); gen_helper_float_roundw_d(fp32, fp64); tcg_temp_free_i64(fp64); - gen_store_fpr32(fp32, fd); + gen_store_fpr32(ctx, fp32, fd); tcg_temp_free_i32(fp32); } opn = "round.w.d"; @@ -7121,7 +7115,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp64, fs); gen_helper_float_truncw_d(fp32, fp64); tcg_temp_free_i64(fp64); - gen_store_fpr32(fp32, fd); + gen_store_fpr32(ctx, fp32, fd); tcg_temp_free_i32(fp32); } opn = "trunc.w.d"; @@ -7135,7 +7129,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp64, fs); gen_helper_float_ceilw_d(fp32, fp64); tcg_temp_free_i64(fp64); - gen_store_fpr32(fp32, fd); + gen_store_fpr32(ctx, fp32, fd); tcg_temp_free_i32(fp32); } opn = "ceil.w.d"; @@ -7149,7 +7143,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp64, fs); gen_helper_float_floorw_d(fp32, fp64); tcg_temp_free_i64(fp64); - gen_store_fpr32(fp32, fd); + gen_store_fpr32(ctx, fp32, fd); tcg_temp_free_i32(fp32); } opn = "floor.w.d"; @@ -7301,7 +7295,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp64, fs); gen_helper_float_cvts_d(fp32, fp64); tcg_temp_free_i64(fp64); - gen_store_fpr32(fp32, fd); + gen_store_fpr32(ctx, fp32, fd); tcg_temp_free_i32(fp32); } opn = "cvt.s.d"; @@ -7315,7 +7309,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp64, fs); gen_helper_float_cvtw_d(fp32, fp64); tcg_temp_free_i64(fp64); - gen_store_fpr32(fp32, fd); + gen_store_fpr32(ctx, fp32, fd); tcg_temp_free_i32(fp32); } opn = "cvt.w.d"; @@ -7336,9 +7330,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, { TCGv_i32 fp0 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); + gen_load_fpr32(ctx, fp0, fs); gen_helper_float_cvts_w(fp0, fp0); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "cvt.s.w"; @@ -7349,7 +7343,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp32 = tcg_temp_new_i32(); TCGv_i64 fp64 = tcg_temp_new_i64(); - gen_load_fpr32(fp32, fs); + gen_load_fpr32(ctx, fp32, fs); gen_helper_float_cvtd_w(fp64, fp32); tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); @@ -7366,7 +7360,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_load_fpr64(ctx, fp64, fs); gen_helper_float_cvts_l(fp32, fp64); tcg_temp_free_i64(fp64); - gen_store_fpr32(fp32, fd); + gen_store_fpr32(ctx, fp32, fd); tcg_temp_free_i32(fp32); } opn = "cvt.s.l"; @@ -7477,7 +7471,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, break; case OPC_MOVCF_PS: check_cp1_64bitmode(ctx); - gen_movcf_ps(fs, fd, (ft >> 2) & 0x7, ft & 0x1); + gen_movcf_ps(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); opn = "movcf.ps"; break; case OPC_MOVZ_PS: @@ -7602,9 +7596,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, { TCGv_i32 fp0 = tcg_temp_new_i32(); - gen_load_fpr32h(fp0, fs); + gen_load_fpr32h(ctx, fp0, fs); gen_helper_float_cvts_pu(fp0, fp0); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "cvt.s.pu"; @@ -7626,9 +7620,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, { TCGv_i32 fp0 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); + gen_load_fpr32(ctx, fp0, fs); gen_helper_float_cvts_pl(fp0, fp0); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "cvt.s.pl"; @@ -7639,10 +7633,10 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); - gen_load_fpr32(fp1, ft); - gen_store_fpr32h(fp0, fd); - gen_store_fpr32(fp1, fd); + gen_load_fpr32(ctx, fp0, fs); + gen_load_fpr32(ctx, fp1, ft); + gen_store_fpr32h(ctx, fp0, fd); + gen_store_fpr32(ctx, fp1, fd); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); } @@ -7654,10 +7648,10 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); - gen_load_fpr32h(fp1, ft); - gen_store_fpr32(fp1, fd); - gen_store_fpr32h(fp0, fd); + gen_load_fpr32(ctx, fp0, fs); + gen_load_fpr32h(ctx, fp1, ft); + gen_store_fpr32(ctx, fp1, fd); + gen_store_fpr32h(ctx, fp0, fd); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); } @@ -7669,10 +7663,10 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); - gen_load_fpr32h(fp0, fs); - gen_load_fpr32(fp1, ft); - gen_store_fpr32(fp1, fd); - gen_store_fpr32h(fp0, fd); + gen_load_fpr32h(ctx, fp0, fs); + gen_load_fpr32(ctx, fp1, ft); + gen_store_fpr32(ctx, fp1, fd); + gen_store_fpr32h(ctx, fp0, fd); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); } @@ -7684,10 +7678,10 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv_i32 fp1 = tcg_temp_new_i32(); - gen_load_fpr32h(fp0, fs); - gen_load_fpr32h(fp1, ft); - gen_store_fpr32(fp1, fd); - gen_store_fpr32h(fp0, fd); + gen_load_fpr32h(ctx, fp0, fs); + gen_load_fpr32h(ctx, fp1, ft); + gen_store_fpr32(ctx, fp1, fd); + gen_store_fpr32h(ctx, fp0, fd); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); } @@ -7763,7 +7757,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx); tcg_gen_trunc_tl_i32(fp0, t0); - gen_store_fpr32(fp0, fd); + gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } opn = "lwxc1"; @@ -7798,7 +7792,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, TCGv_i32 fp0 = tcg_temp_new_i32(); TCGv t1 = tcg_temp_new(); - gen_load_fpr32(fp0, fs); + gen_load_fpr32(ctx, fp0, fs); tcg_gen_extu_i32_tl(t1, fp0); tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); tcg_temp_free_i32(fp0); @@ -7859,24 +7853,24 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, tcg_gen_andi_tl(t0, t0, 0x7); tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0, l1); - gen_load_fpr32(fp, fs); - gen_load_fpr32h(fph, fs); - gen_store_fpr32(fp, fd); - gen_store_fpr32h(fph, fd); + gen_load_fpr32(ctx, fp, fs); + gen_load_fpr32h(ctx, fph, fs); + gen_store_fpr32(ctx, fp, fd); + gen_store_fpr32h(ctx, fph, fd); tcg_gen_br(l2); gen_set_label(l1); tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2); tcg_temp_free(t0); #ifdef TARGET_WORDS_BIGENDIAN - gen_load_fpr32(fp, fs); - gen_load_fpr32h(fph, ft); - gen_store_fpr32h(fp, fd); - gen_store_fpr32(fph, fd); + gen_load_fpr32(ctx, fp, fs); + gen_load_fpr32h(ctx, fph, ft); + gen_store_fpr32h(ctx, fp, fd); + gen_store_fpr32(ctx, fph, fd); #else - gen_load_fpr32h(fph, fs); - gen_load_fpr32(fp, ft); - gen_store_fpr32(fph, fd); - gen_store_fpr32h(fp, fd); + gen_load_fpr32h(ctx, fph, fs); + gen_load_fpr32(ctx, fp, ft); + gen_store_fpr32(ctx, fph, fd); + gen_store_fpr32h(ctx, fp, fd); #endif gen_set_label(l2); tcg_temp_free_i32(fp); @@ -7891,13 +7885,13 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, TCGv_i32 fp1 = tcg_temp_new_i32(); TCGv_i32 fp2 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); - gen_load_fpr32(fp1, ft); - gen_load_fpr32(fp2, fr); + gen_load_fpr32(ctx, fp0, fs); + gen_load_fpr32(ctx, fp1, ft); + gen_load_fpr32(ctx, fp2, fr); gen_helper_float_muladd_s(fp2, fp0, fp1, fp2); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); - gen_store_fpr32(fp2, fd); + gen_store_fpr32(ctx, fp2, fd); tcg_temp_free_i32(fp2); } opn = "madd.s"; @@ -7946,13 +7940,13 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, TCGv_i32 fp1 = tcg_temp_new_i32(); TCGv_i32 fp2 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); - gen_load_fpr32(fp1, ft); - gen_load_fpr32(fp2, fr); + gen_load_fpr32(ctx, fp0, fs); + gen_load_fpr32(ctx, fp1, ft); + gen_load_fpr32(ctx, fp2, fr); gen_helper_float_mulsub_s(fp2, fp0, fp1, fp2); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); - gen_store_fpr32(fp2, fd); + gen_store_fpr32(ctx, fp2, fd); tcg_temp_free_i32(fp2); } opn = "msub.s"; @@ -8001,13 +7995,13 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, TCGv_i32 fp1 = tcg_temp_new_i32(); TCGv_i32 fp2 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); - gen_load_fpr32(fp1, ft); - gen_load_fpr32(fp2, fr); + gen_load_fpr32(ctx, fp0, fs); + gen_load_fpr32(ctx, fp1, ft); + gen_load_fpr32(ctx, fp2, fr); gen_helper_float_nmuladd_s(fp2, fp0, fp1, fp2); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); - gen_store_fpr32(fp2, fd); + gen_store_fpr32(ctx, fp2, fd); tcg_temp_free_i32(fp2); } opn = "nmadd.s"; @@ -8056,13 +8050,13 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, TCGv_i32 fp1 = tcg_temp_new_i32(); TCGv_i32 fp2 = tcg_temp_new_i32(); - gen_load_fpr32(fp0, fs); - gen_load_fpr32(fp1, ft); - gen_load_fpr32(fp2, fr); + gen_load_fpr32(ctx, fp0, fs); + gen_load_fpr32(ctx, fp1, ft); + gen_load_fpr32(ctx, fp2, fr); gen_helper_float_nmulsub_s(fp2, fp0, fp1, fp2); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); - gen_store_fpr32(fp2, fd); + gen_store_fpr32(ctx, fp2, fd); tcg_temp_free_i32(fp2); } opn = "nmsub.s"; @@ -10984,13 +10978,13 @@ static void decode_micromips32_opc (CPUState *env, DisasContext *ctx, case MOVF_FMT: switch (fmt) { case FMT_SDPS_S: - gen_movcf_s(rs, rt, cc, 0); + gen_movcf_s(ctx, rs, rt, cc, 0); break; case FMT_SDPS_D: gen_movcf_d(ctx, rs, rt, cc, 0); break; case FMT_SDPS_PS: - gen_movcf_ps(rs, rt, cc, 0); + gen_movcf_ps(ctx, rs, rt, cc, 0); break; default: goto pool32f_invalid; @@ -10999,13 +10993,13 @@ static void decode_micromips32_opc (CPUState *env, DisasContext *ctx, case MOVT_FMT: switch (fmt) { case FMT_SDPS_S: - gen_movcf_s(rs, rt, cc, 1); + gen_movcf_s(ctx, rs, rt, cc, 1); break; case FMT_SDPS_D: gen_movcf_d(ctx, rs, rt, cc, 1); break; case FMT_SDPS_PS: - gen_movcf_ps(rs, rt, cc, 1); + gen_movcf_ps(ctx, rs, rt, cc, 1); break; default: goto pool32f_invalid;