@@ -149,6 +149,7 @@ typedef struct CPUARMState {
uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
uint32_t c15_threadid; /* TI debugger thread-ID. */
+ uint32_t c15_config_base_address; /* SCU base address. */
} cp15;
struct {
@@ -2111,6 +2111,20 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
* 0x200 << ($rn & 0xfff), when MMU is off. */
goto bad_reg;
}
+ if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
+ switch (crm) {
+ case 0:
+ /* The config_base_address should hold the value of
+ * the peripheral base. ARM should get this from a CPU
+ * object property, but that support isn't available in
+ * December 2011. Default to 0 for now and board models
+ * that care can set it by a private hook */
+ if ((op1 == 4) && (op2 == 0)) {
+ return env->cp15.c15_config_base_address;
+ }
+ }
+ goto bad_reg;
+ }
return 0;
}
bad_reg:
Add a cp15 config_base_register that currently defaults to 0. After the QOM CPU support is added, the value will be properly set to the periphal base value. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> --- Changes from v2 Added test against op2 hanges from v1 renamed the register added comments about how it will change when QOM CPUs are added target-arm/cpu.h | 1 + target-arm/helper.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 0 deletions(-)