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[1/3] target-mips: Streamline indexed cp1 memory addressing.

Message ID 1324160506-25183-2-git-send-email-rth@twiddle.net
State New
Headers show

Commit Message

Richard Henderson Dec. 17, 2011, 10:21 p.m. UTC 
We've already eliminated both base and index being zero.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-mips/translate.c |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)
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Patch

diff --git a/target-mips/translate.c b/target-mips/translate.c
index d5b1c76..b20a817 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -7749,8 +7749,7 @@  static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
     } else if (index == 0) {
         gen_load_gpr(t0, base);
     } else {
-        gen_load_gpr(t0, index);
-        gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
+        gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]);
     }
     /* Don't do NOP if destination is zero: we must perform the actual
        memory access. */