From patchwork Tue Oct 18 18:50:30 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 120508 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B5F7BB71BF for ; Wed, 19 Oct 2011 07:18:28 +1100 (EST) Received: from localhost ([::1]:45321 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RGF1V-0006ZB-Jb for incoming@patchwork.ozlabs.org; Tue, 18 Oct 2011 15:08:25 -0400 Received: from eggs.gnu.org ([140.186.70.92]:34545) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RGF16-0005we-Do for qemu-devel@nongnu.org; Tue, 18 Oct 2011 15:08:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RGElQ-0002DP-BB for qemu-devel@nongnu.org; Tue, 18 Oct 2011 14:51:49 -0400 Received: from mail-wy0-f173.google.com ([74.125.82.173]:53655) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RGElP-0002CC-MP for qemu-devel@nongnu.org; Tue, 18 Oct 2011 14:51:48 -0400 Received: by mail-wy0-f173.google.com with SMTP id 15so1034654wyh.4 for ; Tue, 18 Oct 2011 11:51:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=4ckI0+K7WvSyOrZixl0E4p2B5c/upepuk4uBNxuz6ic=; b=kgv5BB57bty7Ll/Qq9aByBdVj2F0fwYVKEOV5HRqk5V/054lgY7KhLMblA/W7YIvvl 6Lz4YyNAKlyWlbCvFtNZsQ+eZuuFAUsbdMpV5q3BrA5zFegZtfYOrOen9GByM7L3jzrq +WknynjPXCUj8X6OkK/4yn2jI4e57wQX9gvvA= Received: by 10.227.170.8 with SMTP id b8mr1301189wbz.79.1318963907008; Tue, 18 Oct 2011 11:51:47 -0700 (PDT) Received: from localhost.localdomain (c-71-227-161-214.hsd1.wa.comcast.net. [71.227.161.214]) by mx.google.com with ESMTPS id 11sm5169602wby.15.2011.10.18.11.51.45 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 18 Oct 2011 11:51:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 18 Oct 2011 11:50:30 -0700 Message-Id: <1318963843-25100-9-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.6.4 In-Reply-To: <1318963843-25100-1-git-send-email-rth@twiddle.net> References: <1318963843-25100-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 74.125.82.173 Cc: blauwirbel@gmail.com Subject: [Qemu-devel] [PATCH 08/21] target-sparc: Undo cpu_fpr rename. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-sparc/translate.c | 56 +++++++++++++++++++++++----------------------- 1 files changed, 28 insertions(+), 28 deletions(-) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index f37dbb1..f8d3bf2 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -68,7 +68,7 @@ static TCGv cpu_tmp0; static TCGv_i32 cpu_tmp32; static TCGv_i64 cpu_tmp64; /* Floating point registers */ -static TCGv_i32 cpu__fpr[TARGET_FPREGS]; +static TCGv_i32 cpu_fpr[TARGET_FPREGS]; static target_ulong gen_opc_npc[OPC_BUF_SIZE]; static target_ulong gen_opc_jump_pc[2]; @@ -131,12 +131,12 @@ static inline void gen_update_fprs_dirty(int rd) /* floating point registers moves */ static TCGv_i32 gen_load_fpr_F(DisasContext *dc, unsigned int src) { - return cpu__fpr[src]; + return cpu_fpr[src]; } static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v) { - tcg_gen_mov_i32(cpu__fpr[dst], v); + tcg_gen_mov_i32(cpu_fpr[dst], v); gen_update_fprs_dirty(dst); } @@ -151,13 +151,13 @@ static TCGv_i64 gen_load_fpr_D(DisasContext *dc, unsigned int src) src = DFPREG(src); #if TCG_TARGET_REG_BITS == 32 - tcg_gen_mov_i32(TCGV_HIGH(ret), cpu__fpr[src]); - tcg_gen_mov_i32(TCGV_LOW(ret), cpu__fpr[src + 1]); + tcg_gen_mov_i32(TCGV_HIGH(ret), cpu_fpr[src]); + tcg_gen_mov_i32(TCGV_LOW(ret), cpu_fpr[src + 1]); #else { TCGv_i64 t = tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(ret, cpu__fpr[src]); - tcg_gen_extu_i32_i64(t, cpu__fpr[src + 1]); + tcg_gen_extu_i32_i64(ret, cpu_fpr[src]); + tcg_gen_extu_i32_i64(t, cpu_fpr[src + 1]); tcg_gen_shli_i64(ret, ret, 32); tcg_gen_or_i64(ret, ret, t); tcg_temp_free_i64(t); @@ -178,9 +178,9 @@ static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v) tcg_gen_mov_i32(cpu__fpu[dst], TCGV_HIGH(v)); tcg_gen_mov_i32(cpu__fpu[dst + 1], TCGV_LOW(v)); #else - tcg_gen_trunc_i64_i32(cpu__fpr[dst + 1], v); + tcg_gen_trunc_i64_i32(cpu_fpr[dst + 1], v); tcg_gen_shri_i64(v, v, 32); - tcg_gen_trunc_i64_i32(cpu__fpr[dst], v); + tcg_gen_trunc_i64_i32(cpu_fpr[dst], v); #endif gen_update_fprs_dirty(dst); @@ -193,37 +193,37 @@ static TCGv_i64 gen_dest_fpr_D(void) static void gen_op_load_fpr_QT0(unsigned int src) { - tcg_gen_st_i32(cpu__fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) + + tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost)); - tcg_gen_st_i32(cpu__fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) + + tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper)); - tcg_gen_st_i32(cpu__fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) + + tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower)); - tcg_gen_st_i32(cpu__fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) + + tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest)); } static void gen_op_load_fpr_QT1(unsigned int src) { - tcg_gen_st_i32(cpu__fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) + + tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost)); - tcg_gen_st_i32(cpu__fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) + + tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper)); - tcg_gen_st_i32(cpu__fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) + + tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower)); - tcg_gen_st_i32(cpu__fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) + + tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest)); } static void gen_op_store_QT0_fpr(unsigned int dst) { - tcg_gen_ld_i32(cpu__fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) + + tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost)); - tcg_gen_ld_i32(cpu__fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) + + tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper)); - tcg_gen_ld_i32(cpu__fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) + + tcg_gen_ld_i32(cpu_fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower)); - tcg_gen_ld_i32(cpu__fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) + + tcg_gen_ld_i32(cpu_fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest)); } @@ -233,10 +233,10 @@ static void gen_move_Q(int rd, int rs) rd = QFPREG(rd); rs = QFPREG(rs); - tcg_gen_mov_i32(cpu__fpr[rd], cpu__fpr[rs]); - tcg_gen_mov_i32(cpu__fpr[rd + 1], cpu__fpr[rs + 1]); - tcg_gen_mov_i32(cpu__fpr[rd + 2], cpu__fpr[rs + 2]); - tcg_gen_mov_i32(cpu__fpr[rd + 3], cpu__fpr[rs + 3]); + tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs]); + tcg_gen_mov_i32(cpu_fpr[rd + 1], cpu_fpr[rs + 1]); + tcg_gen_mov_i32(cpu_fpr[rd + 2], cpu_fpr[rs + 2]); + tcg_gen_mov_i32(cpu_fpr[rd + 3], cpu_fpr[rs + 3]); gen_update_fprs_dirty(rd); } #endif @@ -5260,9 +5260,9 @@ void gen_intermediate_code_init(CPUSPARCState *env) offsetof(CPUState, gregs[i]), gregnames[i]); for (i = 0; i < TARGET_FPREGS; i++) - cpu__fpr[i] = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUState, fpr[i]), - fregnames[i]); + cpu_fpr[i] = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUState, fpr[i]), + fregnames[i]); /* register helpers */