From patchwork Tue Oct 18 18:50:41 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 120499 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9E2E0B6F88 for ; Wed, 19 Oct 2011 06:53:31 +1100 (EST) Received: from localhost ([::1]:46307 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RGF20-00075C-L1 for incoming@patchwork.ozlabs.org; Tue, 18 Oct 2011 15:08:56 -0400 Received: from eggs.gnu.org ([140.186.70.92]:34237) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RGF1D-0005m4-AB for qemu-devel@nongnu.org; Tue, 18 Oct 2011 15:08:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RGElp-0002Ha-OB for qemu-devel@nongnu.org; Tue, 18 Oct 2011 14:52:21 -0400 Received: from mail-ww0-f41.google.com ([74.125.82.41]:59926) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RGElp-0002HD-1E for qemu-devel@nongnu.org; Tue, 18 Oct 2011 14:52:13 -0400 Received: by wwe32 with SMTP id 32so4068782wwe.4 for ; Tue, 18 Oct 2011 11:52:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=JH7PehJQYJcxLp4SoYnqcRmlPfSRbssf+UIM2f2Ace8=; b=Ul0SdIHvXNzKLj1S3b0G9lCkLEFuF0za4Ymo2K3plT6tn/OnG9GKNxJdTC04D2KiiD iopq224RrooDUUIXO46gf5K64Si7zMkbi7daeZb0ctqBs7bi3wPIOSF0KrQF0rF8HE5U h9YksHl9rJZJEViPoLVBdAlM440Xs9ryY3wZs= Received: by 10.216.22.129 with SMTP id t1mr6163280wet.20.1318963931554; Tue, 18 Oct 2011 11:52:11 -0700 (PDT) Received: from localhost.localdomain (c-71-227-161-214.hsd1.wa.comcast.net. [71.227.161.214]) by mx.google.com with ESMTPS id 11sm5169602wby.15.2011.10.18.11.52.09 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 18 Oct 2011 11:52:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 18 Oct 2011 11:50:41 -0700 Message-Id: <1318963843-25100-20-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.6.4 In-Reply-To: <1318963843-25100-1-git-send-email-rth@twiddle.net> References: <1318963843-25100-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 74.125.82.41 Cc: blauwirbel@gmail.com Subject: [Qemu-devel] [PATCH 19/21] target-sparc: Implement FALIGNDATA inline. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This is a relatively simple sequence of shifts. Signed-off-by: Richard Henderson --- target-sparc/helper.h | 1 - target-sparc/translate.c | 32 ++++++++++++++++++++++++++------ target-sparc/vis_helper.c | 12 ------------ 3 files changed, 26 insertions(+), 19 deletions(-) diff --git a/target-sparc/helper.h b/target-sparc/helper.h index ec00436..7626504 100644 --- a/target-sparc/helper.h +++ b/target-sparc/helper.h @@ -125,7 +125,6 @@ DEF_HELPER_1(fqtoi, s32, env) DEF_HELPER_2(fstox, s64, env, f32) DEF_HELPER_2(fdtox, s64, env, f64) DEF_HELPER_1(fqtox, s64, env) -DEF_HELPER_3(faligndata, i64, env, i64, i64) DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 267ac71..591b391 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2343,6 +2343,31 @@ static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left) tcg_temp_free(tmp); } + +static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) +{ + TCGv t1, t2, shift; + + t1 = tcg_temp_new(); + t2 = tcg_temp_new(); + shift = tcg_temp_new(); + + tcg_gen_andi_tl(shift, gsr, 7); + tcg_gen_shli_tl(shift, shift, 3); + tcg_gen_shl_tl(t1, s1, shift); + + /* A shift of 64 does not produce 0 in TCG. Divide this into a + shift of (up to 63) followed by a constant shift of 1. */ + tcg_gen_xori_tl(shift, shift, 63); + tcg_gen_shr_tl(t2, s2, shift); + tcg_gen_shri_tl(t2, t2, 1); + + tcg_gen_or_tl(dst, t1, t2); + + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(shift); +} #endif #define CHECK_IU_FEATURE(dc, FEATURE) \ @@ -4312,12 +4337,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; case 0x048: /* VIS I faligndata */ CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - cpu_src2_64 = gen_load_fpr_D(dc, rs2); - cpu_dst_64 = gen_dest_fpr_D(); - gen_helper_faligndata(cpu_dst_64, cpu_env, - cpu_src1_64, cpu_src2_64); - gen_store_fpr_D(dc, rd, cpu_dst_64); + gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata); break; case 0x04b: /* VIS I fpmerge */ CHECK_FPU_FEATURE(dc, VIS1); diff --git a/target-sparc/vis_helper.c b/target-sparc/vis_helper.c index 7830120..a992c29 100644 --- a/target-sparc/vis_helper.c +++ b/target-sparc/vis_helper.c @@ -41,18 +41,6 @@ target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize) GET_FIELD_SP(pixel_addr, 11, 12); } -uint64_t helper_faligndata(CPUState *env, uint64_t src1, uint64_t src2) -{ - uint64_t tmp; - - tmp = src1 << ((env->gsr & 7) * 8); - /* on many architectures a shift of 64 does nothing */ - if ((env->gsr & 7) != 0) { - tmp |= src2 >> (64 - (env->gsr & 7) * 8); - } - return tmp; -} - #ifdef HOST_WORDS_BIGENDIAN #define VIS_B64(n) b[7 - (n)] #define VIS_W64(n) w[3 - (n)]