From patchwork Tue Oct 18 18:50:39 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 120505 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8BEC4B71CD for ; Wed, 19 Oct 2011 07:07:08 +1100 (EST) Received: from localhost ([::1]:50568 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RGFwC-0001UY-JD for incoming@patchwork.ozlabs.org; Tue, 18 Oct 2011 16:07:00 -0400 Received: from eggs.gnu.org ([140.186.70.92]:34798) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RGF1G-0006GF-9H for qemu-devel@nongnu.org; Tue, 18 Oct 2011 15:08:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RGElk-0002Gg-8O for qemu-devel@nongnu.org; Tue, 18 Oct 2011 14:52:10 -0400 Received: from mail-ww0-f53.google.com ([74.125.82.53]:33121) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RGElj-00029l-LX for qemu-devel@nongnu.org; Tue, 18 Oct 2011 14:52:08 -0400 Received: by mail-ww0-f53.google.com with SMTP id 36so1209775wwi.10 for ; Tue, 18 Oct 2011 11:52:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=efNKyk9bngb1EfcFodHyYiGhWSQraSeJwAcwX5OcU/o=; b=YOGcnB+L7Y5BLGTtPQemi41bWHQqWSSxQVXMLC51ceFpWjhMWvG85Jwg97tUpLPnKQ m6s7BnRAvd4O3kOYA4cBxa66JAoa4TkmMy0WyCu7v51+2C58mT4bjhAh8yzyysbIqd5p U70j8Ngb4IHJHWaFh/orQ5JHByi5xRyJFEoYA= Received: by 10.216.132.90 with SMTP id n68mr988796wei.17.1318963927171; Tue, 18 Oct 2011 11:52:07 -0700 (PDT) Received: from localhost.localdomain (c-71-227-161-214.hsd1.wa.comcast.net. [71.227.161.214]) by mx.google.com with ESMTPS id 11sm5169602wby.15.2011.10.18.11.52.05 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 18 Oct 2011 11:52:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 18 Oct 2011 11:50:39 -0700 Message-Id: <1318963843-25100-18-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.6.4 In-Reply-To: <1318963843-25100-1-git-send-email-rth@twiddle.net> References: <1318963843-25100-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 74.125.82.53 Cc: blauwirbel@gmail.com Subject: [Qemu-devel] [PATCH 17/21] target-sparc: Implement BMASK/BSHUFFLE. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-sparc/helper.h | 1 + target-sparc/translate.c | 28 ++++++++++++++++++++++++---- target-sparc/vis_helper.c | 29 +++++++++++++++++++++++++++++ 3 files changed, 54 insertions(+), 4 deletions(-) diff --git a/target-sparc/helper.h b/target-sparc/helper.h index 4a61b77..ec00436 100644 --- a/target-sparc/helper.h +++ b/target-sparc/helper.h @@ -140,6 +140,7 @@ DEF_HELPER_FLAGS_3(pdist, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64, i64) DEF_HELPER_FLAGS_2(fpack16, TCG_CALL_CONST | TCG_CALL_PURE, i32, i64, i64) DEF_HELPER_FLAGS_3(fpack32, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64, i64) DEF_HELPER_FLAGS_2(fpackfix, TCG_CALL_CONST | TCG_CALL_PURE, i32, i64, i64) +DEF_HELPER_FLAGS_3(bshuffle, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64, i64) #define VIS_HELPER(name) \ DEF_HELPER_FLAGS_2(f ## name ## 16, TCG_CALL_CONST | TCG_CALL_PURE, \ i64, i64, i64) \ diff --git a/target-sparc/translate.c b/target-sparc/translate.c index e955bf3..66107ee 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -1744,6 +1744,20 @@ static void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, gen_store_fpr_D(dc, rd, dst); } +static void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, + void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) +{ + TCGv_i64 dst, src1, src2; + + src1 = gen_load_fpr_D(dc, rs1); + src2 = gen_load_fpr_D(dc, rs2); + dst = gen_dest_fpr_D(); + + gen(dst, cpu_gsr, src1, src2); + + gen_store_fpr_D(dc, rd, dst); +} + static void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) { @@ -4183,8 +4197,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) gen_movl_TN_reg(rd, cpu_dst); break; case 0x019: /* VIS II bmask */ - // XXX - goto illegal_insn; + CHECK_FPU_FEATURE(dc, VIS2); + cpu_src1 = get_src1(insn, cpu_src1); + cpu_src2 = get_src1(insn, cpu_src2); + tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); + tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32); + gen_movl_TN_reg(rd, cpu_dst); + break; case 0x020: /* VIS I fcmple16 */ CHECK_FPU_FEATURE(dc, VIS1); cpu_src1_64 = gen_load_fpr_D(dc, rs1); @@ -4310,8 +4329,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge); break; case 0x04c: /* VIS II bshuffle */ - // XXX - goto illegal_insn; + CHECK_FPU_FEATURE(dc, VIS2); + gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle); + break; case 0x04d: /* VIS I fexpand */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand); diff --git a/target-sparc/vis_helper.c b/target-sparc/vis_helper.c index 40adb47..7830120 100644 --- a/target-sparc/vis_helper.c +++ b/target-sparc/vis_helper.c @@ -470,3 +470,32 @@ uint32_t helper_fpackfix(uint64_t gsr, uint64_t rs2) return ret; } + +uint64 helper_bshuffle(uint64_t gsr, uint64_t src1, uint64_t src2) +{ + union { + uint64_t ll[2]; + uint8_t b[16]; + } s; + VIS64 r; + uint32_t i, mask, host; + + /* Set up S such that we can index across all of the bytes. */ +#ifdef HOST_WORDS_BIGENDIAN + s.ll[0] = src1; + s.ll[1] = src2; + host = 0; +#else + s.ll[1] = src1; + s.ll[0] = src2; + host = 15; +#endif + mask = gsr >> 32; + + for (i = 0; i < 8; ++i) { + unsigned e = (mask >> (28 - i*4)) & 0xf; + r.VIS_B64(i) = s.b[e ^ host]; + } + + return r.ll; +}