From patchwork Tue Oct 18 18:50:38 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 120491 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A7C43B70C0 for ; Wed, 19 Oct 2011 06:22:44 +1100 (EST) Received: from localhost ([::1]:45521 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RGF1b-0006ft-59 for incoming@patchwork.ozlabs.org; Tue, 18 Oct 2011 15:08:31 -0400 Received: from eggs.gnu.org ([140.186.70.92]:34402) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RGF1F-0005uq-Sh for qemu-devel@nongnu.org; Tue, 18 Oct 2011 15:08:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RGEli-0002GS-9Q for qemu-devel@nongnu.org; Tue, 18 Oct 2011 14:52:12 -0400 Received: from mail-ww0-f53.google.com ([74.125.82.53]:33121) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RGElh-00029l-K4 for qemu-devel@nongnu.org; Tue, 18 Oct 2011 14:52:05 -0400 Received: by mail-ww0-f53.google.com with SMTP id 36so1209775wwi.10 for ; Tue, 18 Oct 2011 11:52:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=UKBEpUI8K2pj/TP2Uoy+KZ4yTY/ZEa1DVlrGvb0PAP4=; b=Cui4UAM9P9c0XzFwoggmS/veU7pEARcCGsXd81WeE59XPnPmv2nt1qLIrEww5VbDBw OB2zHxZdFZyFzCDJ02aJTNM8fuHBX8JgO27vjE/U6V+mJSMe9w9wI1aFHoDVW72J7Q6G i9HGfVetFkFc2qRUc75YnH/2l+LjDZqBeFDNs= Received: by 10.227.62.196 with SMTP id y4mr1350747wbh.19.1318963924995; Tue, 18 Oct 2011 11:52:04 -0700 (PDT) Received: from localhost.localdomain (c-71-227-161-214.hsd1.wa.comcast.net. [71.227.161.214]) by mx.google.com with ESMTPS id 11sm5169602wby.15.2011.10.18.11.52.03 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 18 Oct 2011 11:52:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 18 Oct 2011 11:50:38 -0700 Message-Id: <1318963843-25100-17-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.6.4 In-Reply-To: <1318963843-25100-1-git-send-email-rth@twiddle.net> References: <1318963843-25100-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 74.125.82.53 Cc: blauwirbel@gmail.com Subject: [Qemu-devel] [PATCH 16/21] target-sparc: Implement ALIGNADDR* inline. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org While ALIGNADDR was implemented out-of-line, ALIGNADDRL was not implemeneted at all. However, this is a very simple operation so we're better off doing this inline. Signed-off-by: Richard Henderson --- target-sparc/helper.h | 1 - target-sparc/translate.c | 24 ++++++++++++++++++++++-- target-sparc/vis_helper.c | 11 ----------- 3 files changed, 22 insertions(+), 14 deletions(-) diff --git a/target-sparc/helper.h b/target-sparc/helper.h index 5c8d266..4a61b77 100644 --- a/target-sparc/helper.h +++ b/target-sparc/helper.h @@ -17,7 +17,6 @@ DEF_HELPER_2(wrccr, void, env, tl) DEF_HELPER_1(rdcwp, tl, env) DEF_HELPER_2(wrcwp, void, env, tl) DEF_HELPER_FLAGS_2(array8, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl) -DEF_HELPER_3(alignaddr, tl, env, tl, tl) DEF_HELPER_1(popc, tl, tl) DEF_HELPER_4(ldda_asi, void, env, tl, int, int) DEF_HELPER_5(ldf_asi, void, env, tl, int, int, int) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index df82ecc..e955bf3 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2315,6 +2315,20 @@ static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, tcg_temp_free(t1); tcg_temp_free(t2); } + +static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left) +{ + TCGv tmp = tcg_temp_new(); + + tcg_gen_add_tl(tmp, s1, s2); + tcg_gen_andi_tl(dst, tmp, -8); + if (left) { + tcg_gen_neg_tl(tmp, tmp); + } + tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3); + + tcg_temp_free(tmp); +} #endif #define CHECK_IU_FEATURE(dc, FEATURE) \ @@ -4158,11 +4172,17 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) CHECK_FPU_FEATURE(dc, VIS1); cpu_src1 = get_src1(insn, cpu_src1); gen_movl_reg_TN(rs2, cpu_src2); - gen_helper_alignaddr(cpu_dst, cpu_env, cpu_src1, cpu_src2); + gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0); gen_movl_TN_reg(rd, cpu_dst); break; - case 0x019: /* VIS II bmask */ case 0x01a: /* VIS I alignaddrl */ + CHECK_FPU_FEATURE(dc, VIS1); + cpu_src1 = get_src1(insn, cpu_src1); + gen_movl_reg_TN(rs2, cpu_src2); + gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1); + gen_movl_TN_reg(rd, cpu_dst); + break; + case 0x019: /* VIS II bmask */ // XXX goto illegal_insn; case 0x020: /* VIS I fcmple16 */ diff --git a/target-sparc/vis_helper.c b/target-sparc/vis_helper.c index 59ca8d7..40adb47 100644 --- a/target-sparc/vis_helper.c +++ b/target-sparc/vis_helper.c @@ -41,17 +41,6 @@ target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize) GET_FIELD_SP(pixel_addr, 11, 12); } -target_ulong helper_alignaddr(CPUState *env, target_ulong addr, - target_ulong offset) -{ - uint64_t tmp; - - tmp = addr + offset; - env->gsr &= ~7ULL; - env->gsr |= tmp & 7ULL; - return tmp & ~7ULL; -} - uint64_t helper_faligndata(CPUState *env, uint64_t src1, uint64_t src2) { uint64_t tmp;