From patchwork Thu Aug 25 21:45:22 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111676 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 81091B6F7B for ; Fri, 26 Aug 2011 07:46:16 +1000 (EST) Received: from localhost ([::1]:55745 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qwhka-0006Jz-QE for incoming@patchwork.ozlabs.org; Thu, 25 Aug 2011 17:46:12 -0400 Received: from eggs.gnu.org ([140.186.70.92]:43966) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QwhkM-0006Ad-U0 for qemu-devel@nongnu.org; Thu, 25 Aug 2011 17:46:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QwhkL-0000vi-9G for qemu-devel@nongnu.org; Thu, 25 Aug 2011 17:45:58 -0400 Received: from mail-vw0-f45.google.com ([209.85.212.45]:56901) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QwhkI-0000sB-3K for qemu-devel@nongnu.org; Thu, 25 Aug 2011 17:45:55 -0400 Received: by mail-vw0-f45.google.com with SMTP id 17so2689232vws.4 for ; Thu, 25 Aug 2011 14:45:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=q2PrHhYh0ws+MrNcbLmHS3+sdKNRExSYh6O/91hzwkc=; b=JPwVsyExhqcPtk/c/ALquGPo9rVkvZsaFmdbJzTfBhwc1rsHHX+Ok8iNnEM7OsWURA pX5g8FS1Gr4NGnBPwUZCxaGRS+P8hnvHL1kMdF/01Uj2zG6rY8HdfkicznMPOnMptHg+ Xhe/m25jwV4OoQdXf2H244gNhcqOMQTOydkxo= Received: by 10.52.26.163 with SMTP id m3mr374739vdg.82.1314308753622; Thu, 25 Aug 2011 14:45:53 -0700 (PDT) Received: from localhost.localdomain (cpe-66-91-180-197.hawaii.res.rr.com [66.91.180.197]) by mx.google.com with ESMTPS id eq10sm688769vdb.4.2011.08.25.14.45.52 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 25 Aug 2011 14:45:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 25 Aug 2011 11:45:22 -1000 Message-Id: <1314308722-14495-7-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1314308722-14495-1-git-send-email-rth@twiddle.net> References: <1314308722-14495-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.212.45 Subject: [Qemu-devel] [PATCH 6/6] target-alpha: Add high-resolution access to wall clock and an alarm. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The alarm is a fully general one-shot time comparator, which will be usable under Linux as a hrtimer source. It's much more flexible than the RTC source available on real hardware. The wall clock allows the guest access to the host timekeeping. Much like the KVM wall clock source for other guests. Both are accessed via the PALcode Cserve entry point. Signed-off-by: Richard Henderson --- hw/alpha_typhoon.c | 21 ++++++++++++++++++++- target-alpha/cpu.h | 4 ++++ target-alpha/helper.h | 4 ++++ target-alpha/op_helper.c | 15 +++++++++++++++ target-alpha/translate.c | 14 ++++++++++++++ 5 files changed, 57 insertions(+), 1 deletions(-) diff --git a/hw/alpha_typhoon.c b/hw/alpha_typhoon.c index 3637efc..3d30e0e 100644 --- a/hw/alpha_typhoon.c +++ b/hw/alpha_typhoon.c @@ -681,6 +681,16 @@ static void typhoon_set_timer_irq(void *opaque, int irq, int level) } } +static void typhoon_alarm_timer(void *opaque) +{ + TyphoonState *s = (TyphoonState *)((uintptr_t)opaque & ~3); + int cpu = (uintptr_t)opaque & 3; + + /* Set the ITI bit for this cpu. */ + s->cchip.misc |= 1 << (cpu + 4); + cpu_interrupt(s->cchip.cpu[cpu], CPU_INTERRUPT_TIMER); +} + PCIBus *typhoon_init(ram_addr_t ram_size, qemu_irq *p_rtc_irq, CPUState *cpus[4], pci_map_irq_fn sys_map_irq) { @@ -692,6 +702,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, qemu_irq *p_rtc_irq, PCIHostState *p; TyphoonState *s; PCIBus *b; + int i; dev = qdev_create(NULL, "typhoon-pcihost"); qdev_init_nofail(dev); @@ -700,7 +711,15 @@ PCIBus *typhoon_init(ram_addr_t ram_size, qemu_irq *p_rtc_irq, s = container_of(p, TyphoonState, host); /* Remember the CPUs so that we can deliver interrupts to them. */ - memcpy(s->cchip.cpu, cpus, 4 * sizeof(CPUState *)); + for (i = 0; i < 4; i++) { + CPUState *env = cpus[i]; + s->cchip.cpu[i] = env; + if (env) { + env->alarm_timer = qemu_new_timer_ns(rtc_clock, + typhoon_alarm_timer, + (void *)((uintptr_t)s + i)); + } + } *p_rtc_irq = *qemu_allocate_irqs(typhoon_set_timer_irq, s, 1); diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index c2e7bb3..9d61d45 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -265,6 +265,10 @@ struct CPUAlphaState { uint64_t scratch[24]; #endif + /* This alarm doesn't exist in real hardware; we wish it did. */ + struct QEMUTimer *alarm_timer; + uint64_t alarm_expire; + #if TARGET_LONG_BITS > HOST_LONG_BITS /* temporary fixed-point registers * used to emulate 64 bits target on 32 bits hosts diff --git a/target-alpha/helper.h b/target-alpha/helper.h index c352c24..b693cee 100644 --- a/target-alpha/helper.h +++ b/target-alpha/helper.h @@ -113,7 +113,11 @@ DEF_HELPER_2(stq_c_phys, i64, i64, i64) DEF_HELPER_FLAGS_0(tbia, TCG_CALL_CONST, void) DEF_HELPER_FLAGS_1(tbis, TCG_CALL_CONST, void, i64) + DEF_HELPER_1(halt, void, i64); + +DEF_HELPER_FLAGS_0(get_time, TCG_CALL_CONST, i64) +DEF_HELPER_FLAGS_1(set_alarm, TCG_CALL_CONST, void, i64) #endif #include "def-helper.h" diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c index db5b9e7..6832163 100644 --- a/target-alpha/op_helper.c +++ b/target-alpha/op_helper.c @@ -1228,6 +1228,21 @@ void helper_halt(uint64_t restart) qemu_system_shutdown_request(); } } + +uint64_t helper_get_time(void) +{ + return qemu_get_clock_ns(rtc_clock); +} + +void helper_set_alarm(uint64_t expire) +{ + if (expire) { + env->alarm_expire = expire; + qemu_mod_timer(env->alarm_timer, expire); + } else { + qemu_del_timer(env->alarm_timer); + } +} #endif /*****************************************************************************/ diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 842f915..37f2f20 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -1590,6 +1590,9 @@ static int cpu_pr_data(int pr) return offsetof(CPUAlphaState, shadow[pr - 32]); case 40 ... 63: return offsetof(CPUAlphaState, scratch[pr - 40]); + + case 251: + return offsetof(CPUAlphaState, alarm_expire); } return 0; } @@ -1604,6 +1607,12 @@ static void gen_mfpr(int ra, int regno) return; } + if (regno == 250) { + /* WALL_TIME */ + gen_helper_get_time(cpu_ir[ra]); + return; + } + /* The basic registers are data only, and unknown registers are read-zero, write-ignore. */ if (data == 0) { @@ -1650,6 +1659,11 @@ static ExitStatus gen_mtpr(DisasContext *ctx, int rb, int regno) gen_helper_halt(tmp); return EXIT_PC_STALE; + case 251: + /* ALARM */ + gen_helper_set_alarm(tmp); + break; + default: /* The basic registers are data only, and unknown registers are read-zero, write-ignore. */